公开(公告)号：WO2005112395A1

公开(公告)日：2005-11-24

申请号：PCT/US2005/013234

申请日：2005-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  KANIZ, Marufa, Kaniz ,  DWORK, Jeffrey ,  WILLIAMS, Robert, Alan ,  MANIAR, Mohammad ,  VISWANATH, Somnath

Inventor： KANIZ, Marufa, Kaniz ,  DWORK, Jeffrey ,  WILLIAMS, Robert, Alan ,  MANIAR, Mohammad ,  VISWANATH, Somnath

IPC: H04L29/06

CPC classification number: H04L49/90 ,  H04L63/0485 ,  H04L63/164

Abstract: One aspect of the invention relates to a network interface system (2) for interfacing a host system with a network (8). The network interface system (2) includes a bus interface system (4), a media access control system (10), and a security system (14). The security system (14) selectively perform security processing on data incoming from the network (8) based on security associations stored in a memory external to the network interface system (2), typically a host system memory (128). The security association for any given frame, when available, is fetched from the external memory (128) after the frame begins to arrive in the network interface system (2) based in part on information contained in the frame. Preferably, the fetch begins before the frame is fully received and the security association is queued whereby security processing can begin without having to wait for the security association to be fetched.

Abstract translation: 本发明的一个方面涉及一种用于将主机系统与网络（8）进行接口的网络接口系统（2）。 网络接口系统（2）包括总线接口系统（4），媒体接入控制系统（10）和安全系统（14）。 安全系统（14）基于存储在网络接口系统（2）外部的存储器（通常是主机系统存储器）中的安全关联，有选择地对从网络输入的数据执行安全处理。 部分基于包含在帧中的信息，帧开始到达网络接口系统（2）之后，任何给定帧的安全关联（在可用时）从外部存储器（128）获取。 优选地，在帧被完全接收之前开始，并且安全关联被排队，由此可以开始安全处理而不必等待获取安全关联。

公开(公告)号：WO2005086461A1

公开(公告)日：2005-09-15

申请号：PCT/US2005/005902

申请日：2005-02-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  KANIZ, Marufa ,  DWORK, Jeffrey ,  WILLIAMS, Robert, Alan ,  MANIAR, Mohammad, Y. ,  VISWANATH, Somnath

Inventor： KANIZ, Marufa ,  DWORK, Jeffrey ,  WILLIAMS, Robert, Alan ,  MANIAR, Mohammad, Y. ,  VISWANATH, Somnath

IPC: H04L29/06

CPC classification number: H04L63/0485 ,  H04L63/164

Abstract: The invention relates to a network interface system (2) for interfacing a host system (6) with a network (8). The network interface system (2) includes a bus interface system (6), a media access control system (10), and a security system (14). The network interface (2) offloads IPsec processing from the host system (6). According to the invention, the security system (14) includes two processors (20, 2l.) for encrypting the outgoing data. Outgoing data packets are sent alternately to one or the other processor (20, 21), whereby transmission processing can be accelerated relative to receive processing.

Abstract translation: 本发明涉及一种用于将主机系统（6）与网络（8）进行接口的网络接口系统（2）。 网络接口系统（2）包括总线接口系统（6），媒体接入控制系统（10）和安全系统（14）。 网络接口（2）从主机系统（6）卸载IPsec处理。 根据本发明，安全系统（14）包括用于加密输出数据的两个处理器（20,21）。 输出数据分组被交替地发送到一个或另一个处理器（20,21），从而相对于接收处理可以加速传输处理。

公开(公告)号：WO1997047116A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001858

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ROY, Rajat ,  DWORK, Jeffrey ,  FISCHER, Jenny, Liu

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L12/40013 ,  H04L12/413 ,  H04L49/90

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller (14). The data structure includes the data to be transmitted (58, 60, 76, 82), the STATUS information (62, 84) of the data to be transmitted, and the DESCRIPTOR information (64, 86) of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32-bit STATUS information is organized in four 8-bit bytes in a 32-bit row, and the 32-bit DESCRIPTOR information is organized in four 8-bit bytes in a 32-bit row. A one-bit tag field (66, 72) is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

Abstract translation: 一种在以太网控制器（14）的发送部分中提供高性能的数据结构。 数据结构包括待发送的数据（58,60,76,82），要发送的数据的状态信息（62,84）和要发送的数据的DESCRIPTOR信息（64,86）。 数据以32位行的8位字节组织，32位STATUS信息以32位行的四个8位字节组织，32位DESCRIPTOR信息组织在四位8位 32位行中的字节。 一比特标签字段（66,72）与每个行相关联，并且标签字段中的1表示分组结束位于与该标签相关联的行中。 STATUS字节的低4位包含指示该行中哪个字节包含数据包结束的信息。

公开(公告)号：EP1236091B1

公开(公告)日：2004-01-02

申请号：EP00942687.5

申请日：2000-06-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： DWORK, Jeffrey

IPC: G06F9/30

CPC classification number: G06F9/30098

Abstract: A register arrangement that enables a host CPU to optimize its accesses to registers in a network interface in order to reduce the impact of such accesses on the CPU performance. Registers that must frequently be read by the CPU are combined into a first group and assigned with consecutive addresses corresponding to one end of the register address range. Registers that must frequently be written by the CPU are grouped into a second group and assigned with consecutive addresses corresponding to the opposite end of the register address range. Registers that must frequently be both read and written by the CPU are combined into a third group and assigned with consecutive addresses between the addresses of the first group and addresses of the second group.

公开(公告)号：EP1236091A1

公开(公告)日：2002-09-04

申请号：EP00942687.5

申请日：2000-06-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： DWORK, Jeffrey

IPC: G06F9/30

CPC classification number: G06F9/30098

Abstract: A register arrangement that enables a host CPU to optimize its accesses to registers in a network interface in order to reduce the impact of such accesses on the CPU performance. Registers that must frequently be read by the CPU are combined into a first group and assigned with consecutive addresses corresponding to one end of the register address range. Registers that must frequently be written by the CPU are grouped into a second group and assigned with consecutive addresses corresponding to the opposite end of the register address range. Registers that must frequently be both read and written by the CPU are combined into a third group and assigned with consecutive addresses between the addresses of the first group and addresses of the second group.

公开(公告)号：EP0903029A1

公开(公告)日：1999-03-24

申请号：EP97905784.0

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ROY, Rajat ,  DWORK, Jeffrey ,  FISCHER, Jenny, Liu

IPC: G06F13 ,  F25J1 ,  F25J3 ,  H04L12 ,  H04L29

CPC classification number: H04L29/06 ,  H04L12/40013 ,  H04L12/413 ,  H04L49/90

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller (14). The data structure includes the data to be transmitted (58, 60, 76, 82), the STATUS information (62, 84) of the data to be transmitted, and the DESCRIPTOR information (64, 86) of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32-bit STATUS information is organized in four 8-bit bytes in a 32-bit row, and the 32-bit DESCRIPTOR information is organized in four 8-bit bytes in a 32-bit row. A one-bit tag field (66, 72) is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

公开(公告)号：EP0903029B1

公开(公告)日：2004-05-19

申请号：EP97905784.1

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ROY, Rajat ,  DWORK, Jeffrey ,  FISCHER, Jenny, Liu

IPC: H04L29/06 ,  H04L12/413

CPC classification number: H04L29/06 ,  H04L12/40013 ,  H04L12/413 ,  H04L49/90

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller (14). The data structure includes the data to be transmitted (58, 60, 76, 82), the STATUS information (62, 84) of the data to be transmitted, and the DESCRIPTOR information (64, 86) of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32-bit STATUS information is organized in four 8-bit bytes in a 32-bit row, and the 32-bit DESCRIPTOR information is organized in four 8-bit bytes in a 32-bit row. A one-bit tag field (66, 72) is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.