公开(公告)号：WO2005078791A1

公开(公告)日：2005-08-25

申请号：PCT/US2004/042855

申请日：2004-12-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

Inventor： LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

IPC: H01L21/8246

CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

Abstract translation: 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层（608）的一部分形成在衬底（602）上，并且在电荷俘获电介质层（608）的部分上形成抗蚀剂（614）。 对抗蚀剂（614）进行图案化，并且以一定角度执行凹穴注入（630）以在衬底（602）内建立凹穴注入（620）。 然后执行位线植入（634）以在衬底（602）内建立掩埋位线（640）。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层（608）。 字线材料（660）形成在电荷俘获电介质层的剩余部分上并被图案化以形成覆盖在位线（640）上的字线（662）。 口袋植入物（620）用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

公开(公告)号：WO1997001172A1

公开(公告)日：1997-01-09

申请号：PCT/US1996010562

申请日：1996-06-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HADDAD, Sameer ,  CHANG, Chi ,  LIU, David, K., Y.

IPC: G11C16/06

CPC classification number: G11C16/10

Abstract: Disclosed herein is a channel hot-carrier page write method including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 mu S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps (272), operated from a single +Vcc source. In a preferred embodiment, a cache memory (262) buffers data transfers between a computer bus (264) and the page oriented storage array (252). In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10 to 10 at drain voltages below 5.2VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

Abstract translation: 这里公开了一种通道热载体页写入方法，其包括以非常低能量编程模式操作的堆叠栅极快闪EEPROM存储器单元的阵列，允许在20-100μs编程间隔内进行1024位的写入。 内部编程电压电平源自片上电路，例如从单个+ Vcc源运行的电荷泵（272）。 在优选实施例中，高速缓冲存储器（262）缓冲计算机总线（264）和面向页面的存储阵列（252）之间的数据传输。 在另一个实施例中，在沟道和漏极区域中增加了芯掺杂以增强热载流子注入并降低编程漏极电压。 堆叠的浮置栅极结构在低于5.2VDC的漏极电压下显示出在10 -6至10 -4的范围内的高编程效率。 在另一个实施例中，通过在编程周期开始时对公共源极线进行预充电来最小化编程电流的AC分量。

公开(公告)号：WO2002089144A1

公开(公告)日：2002-11-07

申请号：PCT/US2001/043730

申请日：2001-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FASTOW, Richard, M. ,  HADDAD, Sameer ,  CLEVELAND, Lee

IPC: G11C16/34

CPC classification number: G11C16/3422 ,  G11C16/344 ,  G11C16/3445

Abstract: A technique is provided for reducing column leakage in a flash EEPROM device (10) during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells (100) are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other V th compacting schemes.

Abstract translation: 提供了一种用于在擦除验证过程期间减少快闪EEPROM装置（10）中的列泄漏的技术，从而防止虚假验证。 该技术在NOR阵列或其他类型的阵列中的应用，其中多个单元（100）并联连接。 该技术通过减少未被选择的小区的泄漏与所验证的所选择的小区并行地进行操作，从而防止虚假验证。 该技术还可以与减少列泄漏的其他技术结合使用，例如软编程，自动编程干扰擦除（APDE）或各种其他Vth压缩方案。

公开(公告)号：WO1997049089A1

公开(公告)日：1997-12-24

申请号：PCT/US1997005218

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

Abstract translation: 本发明有助于编程所选择的浮动栅极器件，同时成功地禁止对未选择器件的编程，而不需要生长多个厚度的氧化物。 本发明的优选实施例利用多选择栅极器件。 特别地，选择栅极器件优选地是双浮置栅极器件，而不是在当前闪存存储器系统中用作选择栅极器件的常规晶体管（或用作常规晶体管的器件）。

公开(公告)号：WO2005038810A1

公开(公告)日：2005-04-28

申请号：PCT/US2004/030415

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

Abstract translation: 存储单元阵列（50）包括制造在半导体衬底（54）上的存储单元（52）的二维阵列。 存储单元（52）被布置成限定行方向（67）和限定列方向（69）的多列的多行。 每列存储单元（52）包括多个交替沟道区（58）和源/漏区（64）。 导电互连（72）位于每个源/漏区（64）上方并且仅耦合到另一个源极/漏极区（64）。 另一个源极/漏极区域（64）位于与该列相邻的第二列中。 导电互连（64）被定位成使得每隔一个导电互连（64）连接到列的右侧的相邻列，并且每隔一个导电互连连接到列的左侧的相邻列。 多个源极/漏极控制线（70）在相邻列的存储器单元（52）之间延伸并且电耦合到在相邻列之间耦合的每个导电互连（72）。

公开(公告)号：WO2002091387A1

公开(公告)日：2002-11-14

申请号：PCT/US2002/004784

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FASTOW, Richard, M. ,  GUO, Xin ,  HADDAD, Sameer

IPC: G11C16/34

CPC classification number: G11C16/3409 ,  G11C16/3404

Abstract: A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design are disclosed. The threshold voltage is compacted by erasing (602) a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying (604) at least one fast-erase memory cell; selectively soft-programming (606) the memory cells; and erasing (608) subsequent to selectively soft-programming.

Abstract translation: 公开了具有紧凑的阈值电压分布的快闪存储器设计和用于压缩闪存设计的阈值电压的方法。 通过擦除（602）多个存储器单元来将阈值电压压缩，以将存储器单元的阈值电压基本上朝向中值擦除阈值电压; 验证（604）至少一个快速擦除存储器单元; 选择性地软编程（606）存储器单元; 以及在选择性软编程之后擦除（608）。

公开(公告)号：WO1996026522A1

公开(公告)日：1996-08-29

申请号：PCT/US1995016805

申请日：1995-12-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HADDAD, Sameer ,  FANG, Hao

IPC: G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

Abstract translation: 提供了用于批量（或字节）编程闪存EEPROM存储器单元阵列的改进方法。 对阵列的衬底施加负电压。 将零编程的参考电压同时施加到要编程的所选存储单元的漏极区域。 同时也向所选择的存储器单元的控制栅极同时施加零伏特的相同参考电压。 本发明提供了仅需要单个低电压电源的存储单元的低电流消耗和快速编程。 耐久可靠性大于100,000次。

公开(公告)号：WO2008033332A2

公开(公告)日：2008-03-20

申请号：PCT/US2007/019710

申请日：2007-09-10

Applicant: ADVANCED MICRO DEVICES, INC. ,  SPANSION LLC ,  PANGRLE, Suzette, K. ,  AVANZINO, Steven ,  HADDAD, Sameer ,  VANBUSKIRK, Michael ,  RATHOR, Manuj ,  XIE, James ,  SONG, Kevin ,  MARRIAN, Christie ,  CHOO, Bryan ,  WANG, Fei ,  SHIELDS, Jeffrey, A.

Inventor： PANGRLE, Suzette, K. ,  AVANZINO, Steven ,  HADDAD, Sameer ,  VANBUSKIRK, Michael ,  RATHOR, Manuj ,  XIE, James ,  SONG, Kevin ,  MARRIAN, Christie ,  CHOO, Bryan ,  WANG, Fei ,  SHIELDS, Jeffrey, A.

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer (110), providing an opening (1 12) in the dielectric layer (110), providing a first conductive body ( 116A) in the opening (112), providing a switching body ( 118A) in the opening (112), the first conductive body ( 116A) and switching body (118A) filling the opening (112), and providing a second conductive body (120A) over the switching body (118A). In an alternate embodiment, a second dielectric layer (150) is provided over the first-mentioned dielectric layer (110), and the switching body (156A) is provided in an opening (152) in the second dielectric layer (150).

Abstract translation: 制造存储器件的当前方法包括以下步骤：提供介电层（110），在介电层（110）中提供开口（112），提供第一导电体（116A ）在开口（112）中，在开口（112）中提供切换主体（118A），第一导电主体（116A）和开关主体（118A）填充开口（112），并且提供第二导电主体（120A ）在切换体（118A）上方。 在替代实施例中，在第一介电层（110）上提供第二介电层（150），并且在第二介电层（150）中的开口（152）中提供开关体（156A） / p>

公开(公告)号：WO2005114734A1

公开(公告)日：2005-12-01

申请号：PCT/US2005/004540

申请日：2005-02-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  QIAN, Weidon ,  RAMSBEY, Mark, T. ,  YANG, Jean, Yee-Mei ,  HADDAD, Sameer

Inventor： QIAN, Weidon ,  RAMSBEY, Mark, T. ,  YANG, Jean, Yee-Mei ,  HADDAD, Sameer

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: The present invention pertains to implementing a dual poly process (500) in forming a transistor based memory device (600). The process allows buried bitlines (662) to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials (670, 674) are also formed over the buried bitlines (662) to improve ( e . g ., increase) a breakdown voltage between the bitlines (662) and wordlines (678), thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process (500) also facilitates a reduction in buried bitline width (666) and thus allows bitlines (662) to be formed closer together. As a result, more devices can be "packed" within the same or a smaller area.

Abstract translation: 本发明涉及在形成基于晶体管的存储器件（600）中实施双重聚合工艺（500）。 该过程允许以比传统位线更少的能量和更浅的深度形成掩埋位线（662），以节省资源和空间，并且改善Vt滚降。 氧化物材料（670,674）也形成在掩埋位线（662）上以改善（例如，增加）位线（662）和字线（678）之间的击穿电压，从而允许编程和擦除电荷之间的更大区分， 更可靠的结果数据存储。 过程（500）还有助于减少掩埋位线宽度（666），从而允许位线（662）更靠近地形成。 因此，更多的设备可以在相同或较小的区域内“打包”。

公开(公告)号：WO2004073058A2

公开(公告)日：2004-08-26

申请号：PCT/US2004/000493

申请日：2004-01-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  HE, Yue-Song ,  HADDAD, Sameer ,  WANG, Zhigang

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  WANG, Zhigang

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273

Abstract: In a method of fabricating a semiconductor device, a gate oxide layer (60) is provided on a silicon substrate (62). A first polysilicon layer (64) is provided on the gate oxide layer (60), a dielectric layer (66) is provided on the first polysilicon layer (64), and a second polysilicon layer (68) is provided on the dielectric layer (66). Upon appropriate masking, en etch step is undertaken, etching the second polysilicon layer (68), dielectric layer (66), first polysilicon layer (64) and gate oxide layer (60) to remove portions thereof to expose the silicon substrate (62) and to form a stacked gate structure (72) on the silicon substrate (62). A rapid thermal anneal is undertaken for a short period time, i.e., for example 10-20 seconds, to grow a thin oxide layer (80) on the stacked gate structure (72). Then, another oxide layer (82) is deposited over the oxide layer (80) which was formed by rapid thermal anneal.

Abstract translation: 在制造半导体器件的方法中，在硅衬底（62）上设置栅氧化层（60）。 在栅极氧化物层（60）上设置第一多晶硅层（64），在第一多晶硅层（64）上设置电介质层（66），在介电层上设置第二多晶硅层（68） 66）。 在适当的掩蔽下，进行蚀刻步骤，蚀刻第二多晶硅层（68），电介质层（66），第一多晶硅层（64）和栅极氧化物层（60）以去除其部分以暴露硅衬底（62） 并在硅衬底（62）上形成叠层栅结构（72）。 快速热退火进行短时间，即例如10-20秒，以在堆叠的栅极结构（72）上生长薄的氧化物层（80）。 然后，在通过快速热退火形成的氧化物层（80）上沉积另一氧化物层（82）。