公开(公告)号：WO1996019011A1

公开(公告)日：1996-06-20

申请号：PCT/US1995015299

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, K., Y. ,  GARDNER, Mark, I. ,  HAUSE, Fred

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/823814

Abstract: A method of fabricating a MOS integrated circuit device utilizes high energy, high current implanting of ions through a layer of oxide to form heavily doped source and drain regions which are self-aligned with a polysilicon gate. A thick portion of the oxide layer adjacent to the polysilicon gate prevents heavy doping in the substrate next to the gate. The oxide layer is removed and a liightly doped drain (LDD) implant forms an LDD region which is self-aligned with the gate. Using this method the source/drain and LDD implants are performed using only a single mask and etch operation, rater than two mask and etch operations which are necessary using a conventional process.

Abstract translation: 制造MOS集成电路器件的方法利用高能量，高电流注入离子通过氧化层形成与多晶硅栅极自对准的重掺杂源极和漏极区。 与多晶硅栅极相邻的氧化物层的厚部分防止在栅极旁边的衬底中的重掺杂。 去除氧化物层，并且掺杂稀土的漏极（LDD）注入器形成与栅极自对准的LDD区域。 使用该方法，仅使用单个掩模和蚀刻操作来执行源/漏极和LDD注入，而不是使用常规工艺所必需的两个掩模和蚀刻操作。

公开(公告)号：EP0797842A1

公开(公告)日：1997-10-01

申请号：EP95942891.0

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, K., Y. ,  GARDNER, Mark, I. ,  HAUSE, Fred

IPC: H01L21

CPC classification number: H01L29/6659 ,  H01L21/823814

Abstract: A method of fabricating a MOS integrated circuit device utilizes high energy, high current implanting of ions through a layer of oxide to form heavily doped source and drain regions which are self-aligned with a polysilicon gate. A thick portion of the oxide layer adjacent to the polysilicon gate prevents heavy doping in the substrate next to the gate. The oxide layer is removed and a liightly doped drain (LDD) implant forms an LDD region which is self-aligned with the gate. Using this method the source/drain and LDD implants are performed using only a single mask and etch operation, rater than two mask and etch operations which are necessary using a conventional process.