公开(公告)号：WO2004100230A2

公开(公告)日：2004-11-18

申请号：PCT/US2004/011354

申请日：2004-04-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED ,  FASTOW, Richard ,  HE, Yue-Song ,  MIZUTANI, Kazuhiro ,  THURGATE, Timothy

Inventor： FASTOW, Richard ,  HE, Yue-Song ,  MIZUTANI, Kazuhiro ,  THURGATE, Timothy

IPC: H01L21/00

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing (404) a dielectric material from an isolation region (110) situated in a substrate (258,358) to expose a trench (128,228), where the trench (128,228) is situated between a first source region (116,216,316) and a second source region (118,218), where the trench (128,228) defines sidewalls (150,250) in the substrate (258,358,). The method further comprises implanting (406) an N type dopant in the first source region (116,216,316), the second source region (118,218,318), and the sidewalls (150,250) of the trench (128,228), where the N type dopant forms an N+ type region (252,352). The method further comprises implanting (408) a P type dopant in the first source region (116,216,316), the second source region (118,218), and the sidewalls (150,250) of the trench (128,228), where the P type dopant forms a P type region (256,356), and where the P type region (256,356) is situated underneath the N+ type region (252,352).

Abstract translation: 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底（258,358）中的隔离区（110）去除（404）电介质材料以暴露沟槽（128,228）的步骤，其中 沟槽（128,228）位于第一源极区域（116,216,316）和第二源极区域（118,218）之间，其中沟槽（128,228）限定衬底（258,358）中的侧壁（150,250）。 该方法还包括在第一源区（116,216,316），第二源区（118,218,318）和沟槽（128,228）的侧壁（150,250）中注入（406）N型掺杂剂，其中N型掺杂剂形成N + 类型区域（252,352）。 该方法还包括在第一源区（116,216,316），第二源区（118,218）和沟槽（128,228）的侧壁（150,250）中注入（408）P型掺杂剂，其中P型掺杂剂形成P 类型区域（256,356），并且其中P型区域（256,356）位于N +型区域（252,352）下方。

公开(公告)号：WO2004073058A2

公开(公告)日：2004-08-26

申请号：PCT/US2004/000493

申请日：2004-01-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  HE, Yue-Song ,  HADDAD, Sameer ,  WANG, Zhigang

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  WANG, Zhigang

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273

Abstract: In a method of fabricating a semiconductor device, a gate oxide layer (60) is provided on a silicon substrate (62). A first polysilicon layer (64) is provided on the gate oxide layer (60), a dielectric layer (66) is provided on the first polysilicon layer (64), and a second polysilicon layer (68) is provided on the dielectric layer (66). Upon appropriate masking, en etch step is undertaken, etching the second polysilicon layer (68), dielectric layer (66), first polysilicon layer (64) and gate oxide layer (60) to remove portions thereof to expose the silicon substrate (62) and to form a stacked gate structure (72) on the silicon substrate (62). A rapid thermal anneal is undertaken for a short period time, i.e., for example 10-20 seconds, to grow a thin oxide layer (80) on the stacked gate structure (72). Then, another oxide layer (82) is deposited over the oxide layer (80) which was formed by rapid thermal anneal.

Abstract translation: 在制造半导体器件的方法中，在硅衬底（62）上设置栅氧化层（60）。 在栅极氧化物层（60）上设置第一多晶硅层（64），在第一多晶硅层（64）上设置电介质层（66），在介电层上设置第二多晶硅层（68） 66）。 在适当的掩蔽下，进行蚀刻步骤，蚀刻第二多晶硅层（68），电介质层（66），第一多晶硅层（64）和栅极氧化物层（60）以去除其部分以暴露硅衬底（62） 并在硅衬底（62）上形成叠层栅结构（72）。 快速热退火进行短时间，即例如10-20秒，以在堆叠的栅极结构（72）上生长薄的氧化物层（80）。 然后，在通过快速热退火形成的氧化物层（80）上沉积另一氧化物层（82）。

公开(公告)号：WO2004042808A1

公开(公告)日：2004-05-21

申请号：PCT/US2003/018447

申请日：2003-06-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HE, Yue-Song ,  FASTOW, Richard, M. ,  WANG, Zhi-Gang

IPC: H01L21/28

CPC classification number: H01L29/66825 ,  H01L21/28247 ,  H01L21/28273

Abstract: A method of manufacturing a metal oxide semiconductor (500). A gate structure of the metal oxide semiconductor is etched (510). A nitrogen-comprising gas, which may be NO or N 2 O, is made to flow over the metal oxide semiconductor (500). A pre-implant film (620) is grown over the edges of the gate structure. The pre-implant film may repair damage to a gate stack edge caused by an etching process. The film may be substantially silicon nitride. Beneficially, such a film may be thinner than a conventional silica oxide film. A thinner film does not deleteriously contribute to non-uniformities in a tunnel oxide. A non-uniform tunnel oxide may result in a non-uniform field between a gate and a channel. Non-uniform fields may have numerous deleterious effects. Advantageously, embodiments of the present invention overcome prior art deficiencies in repairing gate stack edge defects. In this novel manner, gate stack edge defects may be physically repaired without deleterious consequences to the electrical behavior of a metal oxide semiconductor device. The novel application of silicon nitride to this application allows thin repair layers to be grown. Advantageously, semiconductors manufactured using embodiments of the present invention may utilize smaller process feature sizes, resulting in denser arrays of semiconductor devices, resulting in lower costs for such devices and realizing a competitive advantage to practitioners of the improvements in the arts herein described.

Abstract translation: 一种制造金属氧化物半导体（500）的方法。 蚀刻金属氧化物半导体的栅极结构（510）。 可以将含氮气体（可以是NO或N2O）流过金属氧化物半导体（500）。 在门结构的边缘上生长预植入膜（620）。 预植入膜可以修复由蚀刻工艺引起的栅堆叠边缘的损坏。 该膜可以基本上是氮化硅。 有利地，这种膜可以比常规二氧化硅膜薄。 更薄的膜对隧道氧化物中的不均匀性没有有害的贡献。 不均匀隧道氧化物可能导致栅极和沟道之间的不均匀场。 非均匀场可能有许多有害影响。 有利地，本发明的实施例克服了修复栅极堆叠边缘缺陷的现有技术缺陷。 以这种新颖的方式，可以物理地修复栅极堆叠边缘缺陷，而不会对金属氧化物半导体器件的电气行为产生有害影响。 氮化硅在该应用中的新颖应用允许生长薄的修复层。 有利地，使用本发明的实施例制造的半导体可以利用较小的工艺特征尺寸，导致更密集的半导体器件的阵列，从而导致这种器件的成本降低，并且实现了本领域技术人员改进的竞争优势。

公开(公告)号：EP1556887A1

公开(公告)日：2005-07-27

申请号：EP03741930.6

申请日：2003-06-10

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HE, Yue-Song ,  FASTOW, Richard, M. ,  WANG, Zhi-Gang

IPC: H01L21/28 ,  H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28247 ,  H01L21/28273

Abstract: A method of manufacturing a metal oxide semiconductor (500). A gate structure of the metal oxide semiconductor is etched (510). A nitrogen-comprising gas, which may be NO or N2O, is made to flow over the metal oxide semiconductor (500). A pre-implant film (620) is grown over the edges of the gate structure. The pre-implant film may repair damage to a gate stack edge caused by an etching process. The film may be substantially silicon nitride. Beneficially, such a film may be thinner than a conventional silica oxide film. A thinner film does not deleteriously contribute to non-uniformities in a tunnel oxide. A non-uniform tunnel oxide may result in a non-uniform field between a gate and a channel. Non-uniform fields may have numerous deleterious effects. Advantageously, embodiments of the present invention overcome prior art deficiencies in repairing gate stack edge defects. In this novel manner, gate stack edge defects may be physically repaired without deleterious consequences to the electrical behavior of a metal oxide semiconductor device. The novel application of silicon nitride to this application allows thin repair layers to be grown. Advantageously, semiconductors manufactured using embodiments of the present invention may utilize smaller process feature sizes, resulting in denser arrays of semiconductor devices, resulting in lower costs for such devices and realizing a competitive advantage to practitioners of the improvements in the arts herein described.

公开(公告)号：EP1338032A2

公开(公告)日：2003-08-27

申请号：EP01990808.6

申请日：2001-10-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  FASTOW, Richard, M. ,  CHANG, Chi ,  WANG, Zhigang ,  PARK, Sheung-Hee

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

Abstract: For fabricating a flash memory cell on a semiconductor substrate, a channel dopant is implanted into the semiconductor substrate. The concentration of the channel dopang in the semiconductor substrate from the implantation process is less than about 4X1013/Cm2. A source line mask is formed over the substrate, and the source link mask has an opening to expose a source line of the semiconductor substrate. A source line dopant of a first conductivity type is implanted into the exposed source line of the semiconductor substrate. The source line mask is then removed from the semiconductor substrate. A drain mask is formed over the semiconductor substrate, and the drain mask has an opening to expose a drain region of the semiconductor substrate. A drain dopant of a second conductivity type is implanted into the exposed drain region of the semiconductor substrate. A channel region of the semiconductor substrate is disposed between the source line and the drain region. The first conductivity type of the source line dopant is opposite to the second conductivity type of the drain dopang. In addition, a conductivity type of the channel dopant is same as the first conductivity type of the source line dopant. The source line dopant that diffuses from the source line into the channel region is used to alter a threshold voltage of the flash memory cell and/or to reduce short channel effects of the flash memory cell such that a lower concentration of the channel dopant is implanted or such that the implantation of the channel dopant is even eliminated, for improved reliability and performance of the flash memory cell.

公开(公告)号：EP1198834A1

公开(公告)日：2002-04-24

申请号：EP00943282.4

申请日：2000-06-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, Kent, Kuohua ,  AU, Kenneth, Wo-Wai ,  HE, Yue-Song

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11546

Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.

公开(公告)号：EP1356505A1

公开(公告)日：2003-10-29

申请号：EP01957475.5

申请日：2001-08-06

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  HE, Yue-Song ,  THURGATE, Timothy ,  CHANG, Chi ,  WONG, Ngaching

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/66833

Abstract: One aspect of the present invention relates to a method of making a flash memory cell (32), involving providing a substrate (30) having a flash memory cell (32) thereon; forming a self-aligned source mask (48) over the substrate, the self aligned source mask (48) having openings (50) corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings (50) in the self-aligned source mask (48) corresponding to source lines (52); removing the self-aligned source mask (48) from the substrate (30); forming a MDD mask (54) over the substrate (30), the MDD mask (54) covering the source lines (52) and having openings (56) corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region (58) in the substrate (30) adjacent the flash memory cell (32).

公开(公告)号：EP1330840A1

公开(公告)日：2003-07-30

申请号：EP01959586.7

申请日：2001-08-06

Applicant: Advanced Micro Devices Inc.

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  THURGATE, Timothy ,  CHANG, Chi

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/66833

Abstract: One aspect of the present invention relates to a method of making a flash memory cell (32) involving the steps of providing a substrate (30) having a flash memory cell (32) thereon; forming a self-aligned source mask (48) over the substrate (30), the self aligned source mask (48) having openings (50) corresponding to source lines; implanting a source dopant of a first type (52) in the substrate (30) through the openings (50) in the self-aligned source mask (48) corresponding to source lines; removing the self-aligned source mask (48) from the substrate (30); cleaning the substrate (30); and implanting a medium dosage drain implant of a second type to form a source region (54) and a drain region (56) in the substrate (30) adjacent the flash memory cell (32).