公开(公告)号：WO2004073058A2

公开(公告)日：2004-08-26

申请号：PCT/US2004/000493

申请日：2004-01-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  HE, Yue-Song ,  HADDAD, Sameer ,  WANG, Zhigang

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  WANG, Zhigang

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273

Abstract: In a method of fabricating a semiconductor device, a gate oxide layer (60) is provided on a silicon substrate (62). A first polysilicon layer (64) is provided on the gate oxide layer (60), a dielectric layer (66) is provided on the first polysilicon layer (64), and a second polysilicon layer (68) is provided on the dielectric layer (66). Upon appropriate masking, en etch step is undertaken, etching the second polysilicon layer (68), dielectric layer (66), first polysilicon layer (64) and gate oxide layer (60) to remove portions thereof to expose the silicon substrate (62) and to form a stacked gate structure (72) on the silicon substrate (62). A rapid thermal anneal is undertaken for a short period time, i.e., for example 10-20 seconds, to grow a thin oxide layer (80) on the stacked gate structure (72). Then, another oxide layer (82) is deposited over the oxide layer (80) which was formed by rapid thermal anneal.

Abstract translation: 在制造半导体器件的方法中，在硅衬底（62）上设置栅氧化层（60）。 在栅极氧化物层（60）上设置第一多晶硅层（64），在第一多晶硅层（64）上设置电介质层（66），在介电层上设置第二多晶硅层（68） 66）。 在适当的掩蔽下，进行蚀刻步骤，蚀刻第二多晶硅层（68），电介质层（66），第一多晶硅层（64）和栅极氧化物层（60）以去除其部分以暴露硅衬底（62） 并在硅衬底（62）上形成叠层栅结构（72）。 快速热退火进行短时间，即例如10-20秒，以在堆叠的栅极结构（72）上生长薄的氧化物层（80）。 然后，在通过快速热退火形成的氧化物层（80）上沉积另一氧化物层（82）。

公开(公告)号：WO2002095762A3

公开(公告)日：2002-11-28

申请号：PCT/US2002/004779

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WANG, Zhigang ,  FASTOW, Richard ,  HADDAD, Sameer ,  PARK, Sheung-Hee ,  CHANG, Chi

IPC: G11C16/10

Abstract: A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.

公开(公告)号：EP1395992A2

公开(公告)日：2004-03-10

申请号：EP02713624.1

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WANG, Zhigang ,  FASTOW, Richard ,  HADDAD, Sameer ,  PARK, Sheung-Hee ,  CHANG, Chi

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

Abstract: A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.

公开(公告)号：EP1338032A2

公开(公告)日：2003-08-27

申请号：EP01990808.6

申请日：2001-10-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  FASTOW, Richard, M. ,  CHANG, Chi ,  WANG, Zhigang ,  PARK, Sheung-Hee

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

Abstract: For fabricating a flash memory cell on a semiconductor substrate, a channel dopant is implanted into the semiconductor substrate. The concentration of the channel dopang in the semiconductor substrate from the implantation process is less than about 4X1013/Cm2. A source line mask is formed over the substrate, and the source link mask has an opening to expose a source line of the semiconductor substrate. A source line dopant of a first conductivity type is implanted into the exposed source line of the semiconductor substrate. The source line mask is then removed from the semiconductor substrate. A drain mask is formed over the semiconductor substrate, and the drain mask has an opening to expose a drain region of the semiconductor substrate. A drain dopant of a second conductivity type is implanted into the exposed drain region of the semiconductor substrate. A channel region of the semiconductor substrate is disposed between the source line and the drain region. The first conductivity type of the source line dopant is opposite to the second conductivity type of the drain dopang. In addition, a conductivity type of the channel dopant is same as the first conductivity type of the source line dopant. The source line dopant that diffuses from the source line into the channel region is used to alter a threshold voltage of the flash memory cell and/or to reduce short channel effects of the flash memory cell such that a lower concentration of the channel dopant is implanted or such that the implantation of the channel dopant is even eliminated, for improved reliability and performance of the flash memory cell.