公开(公告)号：WO2004032246A1

公开(公告)日：2004-04-15

申请号：PCT/US2003/028660

申请日：2003-09-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LIN, Ming-Ren ,  GOO, Jung-Suk ,  WANG, Haihong ,  XIANG, Qi

IPC: H01L29/786

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body (46) is patterned from a layer of silicon germanium (SiGe) (42) that overlies a dielectric layer (40). An epitaxial layer of silicon (34) is then formed on the silicon germanium FinFET body (46). A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract translation: FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体（46）从覆盖在电介质层（40）上的硅锗层（SiGe）（42）构图。 然后在硅锗FinFET体（46）上形成硅（34）的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：WO2004038807A1

公开(公告)日：2004-05-06

申请号：PCT/US2003/028680

申请日：2003-09-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PATON, Eric, N. ,  XIANG, Qi ,  BESSER, Paul, R. ,  LIN, Ming-Ren ,  NGO, Minh, Van ,  WANG, Haihong

IPC: H01L29/78

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide (62, 64) that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

Abstract translation: MOSFET栅极或MOSFET源极或漏极区域包括硅锗或多晶硅锗。 进行镍的硅化以形成优选包含硅化镍的一硅化物相的锗硅酸镍（62,64）。 在硅化物中包含锗提供了可以形成单硅化物相的更宽的温度范围，同时基本上保持了一氧化硅镍表现出的优异的薄层电阻。 因此，在后续处理中，锗硅酸镍能够耐受比一次硅化镍更高的温度，同时提供了与一氧化硅一样的大致相同的薄层电阻和其他有益的性能。

公开(公告)号：WO2004093197A2

公开(公告)日：2004-10-28

申请号：PCT/US2004/009696

申请日：2004-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  LIN, Ming-Ren ,  WANG, Haihong ,  YU, Bin

Inventor： LIN, Ming-Ren ,  WANG, Haihong ,  YU, Bin

IPC: H01L29/00

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A semiconductor device includes a first fin structure (810), a second fin structure (810), and a third fin structure (210). The first and second fin structures (810) include a single-crystal silicon material. The third fin structure (210) is located between the first fin structure (810) and the second fin structure (810) and includes a dielectric material. The third fin structure (210) causes stress to be induced in the single-crystal silicon material of the first fin structure (810) and the second fin structure (810).

Abstract translation: 半导体器件包括第一鳍结构（810），第二鳍结构（810）和第三鳍结构（210）。 第一和第二鳍结构（810）包括单晶硅材料。 第三翅片结构（210）位于第一翅片结构（810）和第二翅片结构（810）之间，并且包括电介质材料。 第三鳍状结构（210）在第一鳍结构（810）和第二鳍结构（810）的单晶硅材料中引起应力。

公开(公告)号：WO2004084299A3

公开(公告)日：2004-09-30

申请号：PCT/US2004/007464

申请日：2004-03-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  WANG, Haihong ,  NGO, Minh, Van ,  XIANG, Qi ,  BESSER, Paul, R. ,  PATON, Eric, N. ,  LIN, Ming-Ren

Inventor： WANG, Haihong ,  NGO, Minh, Van ,  XIANG, Qi ,  BESSER, Paul, R. ,  PATON, Eric, N. ,  LIN, Ming-Ren

IPC: H01L21/762

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

公开(公告)号：WO2004066368A2

公开(公告)日：2004-08-05

申请号：PCT/US2004/000982

申请日：2004-01-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  NGO, Minh-Van ,  XIANG, Qi ,  BESSER, Paul, R. ,  PATON, Eric, N. ,  LIN, Ming-Ren

Inventor： NGO, Minh-Van ,  XIANG, Qi ,  BESSER, Paul, R. ,  PATON, Eric, N. ,  LIN, Ming-Ren

IPC: H01L

CPC classification number: H01L21/76224

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can form the liner.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。 低温过程可以是LPCVD。 退火步骤可以形成衬套。

公开(公告)号：WO2006052379A1

公开(公告)日：2006-05-18

申请号：PCT/US2005/036894

申请日：2005-10-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  XIANG, Qi ,  SUBBA, Niraj ,  MASZARA, Witold, P. ,  KRIVOKAPIC, Zoran ,  LIN, Ming-Ren

Inventor： XIANG, Qi ,  SUBBA, Niraj ,  MASZARA, Witold, P. ,  KRIVOKAPIC, Zoran ,  LIN, Ming-Ren

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate (102) is provided having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104). A deep trench isolation (108) is formed, introducing strain to the semiconductor layer (106). A gate dielectric (202) and a gate (204) are formed on the semiconductor layer (106). A spacer (304) is formed around the gate (204), and the semiconductor layer (106) and the insulator (104) are removed outside the spacer (304). Recessed source/drain (402) are formed outside the spacer (304).

Abstract translation: 提供了一种半导体衬底（102），其上具有绝缘体（104），绝缘体（104）上具有半导体层（106）。 形成深沟槽隔离（108），将应变引入半导体层（106）。 在半导体层（106）上形成栅极电介质（202）和栅极（204）。 在栅极（204）周围形成间隔物（304），并且将半导体层（106）和绝缘体（104）去除在间隔物304的外部。 嵌入式源极/漏极（402）形成在间隔物（304）的外侧。

公开(公告)号：WO2004068586A1

公开(公告)日：2004-08-12

申请号：PCT/US2004/000981

申请日：2004-01-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  NGO, Minh-Van ,  BESSER, Paul, R. ,  LIN, Ming-Ren ,  WANG, Haihong

Inventor： NGO, Minh-Van ,  BESSER, Paul, R. ,  LIN, Ming-Ren ,  WANG, Haihong

IPC: H01L29/10

CPC classification number: H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate (40) having a gate (54) formed above the substrate (40) and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer (60) around a gate (54) and gate insulator (56) located above a layer of silicon (42) above the substrate (40); depositing an etch stop layer (63) above the spacer (60), the gate (54), and the layer of silicon (42); and depositing a dielectric layer (65) above the etch stop layer (63). At least one of the depositing a spacer layer, depositing an etch stop layer (63), and depositing a dielectric layer (65) comprises high compression deposition which increases in tensile strain in the layer of silicon (42).

Abstract translation: 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供具有形成在基底（40）上方的栅极（54）并且执行以下沉积步骤中的至少一个的衬底（40）：沉积间隔层并在栅极（54）周围形成间隔物（60） 和位于所述衬底（40）上方的硅层（42）上方的栅极绝缘体（56）。 在所述间隔物（60）上方，在所述栅极（54）和所述硅层（42）之上沉积蚀刻停止层（63）; 以及在所述蚀刻停止层（63）上沉积介电层（65）。 沉积间隔层，沉积蚀刻停止层（63）和沉积介电层（65）中的至少一个包括增加硅层（42）中的拉伸应变的高压缩沉积。

公开(公告)号：WO1996012297A2

公开(公告)日：1996-04-25

申请号：PCT/US1995012194

申请日：1995-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HUANG, Richard, J. ,  HUI, Angela ,  CHEUNG, Robin ,  CHANG, Mark ,  LIN, Ming-Ren

IPC: H01L21/768

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. An embodiment comprises the simultaneous formation of a via and trench in a single etching step.

Abstract translation: 使用改进的双镶嵌工艺来制造包含具有减小的布线连接间隙的互连结构的半导体器件。 一个实施例是在单个蚀刻步骤中同时产生通孔和沟槽。

公开(公告)号：WO2005109493A1

公开(公告)日：2005-11-17

申请号：PCT/US2005/013240

申请日：2005-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  PAN, James ,  LIN, Ming-Ren

Inventor： PAN, James ,  LIN, Ming-Ren

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842

Abstract: A dual-metal CMOS arrangement and method of making the same provides a substrate (10) and a plurality of NMOS devices (44) and PMOS devices (46) formed on the substrate (10). Each of the plurality of NMOS devices (44) and PMOS devices (46) have gate electrodes. Each NMOS gate electrode includes a first silicide region (50) on the substrate (10) and a first metal region (48) on the first silicide region (50). The first silicide region (50) of the NMOS gate electrode consists of a first silicide (50) having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region (54) on the substrate and a second metal region (52) on the second silicide region (54). The second silicide region (54) of the PMOS gate electrode consists of a second silicide (54) having a work function that is close to the valence band of silicon.

Abstract translation: 双金属CMOS布置及其制造方法提供了形成在衬底（10）上的衬底（10）和多个NMOS器件（44）和PMOS器件（46）。 多个NMOS器件（44）和PMOS器件（46）中的每一个具有栅电极。 每个NMOS栅极包括在基底（10）上的第一硅化物区（50）和第一硅化物区（50）上的第一金属区（48）。 NMOS栅电极的第一硅化物区域（50）由具有接近硅导带的功函数的第一硅化物（50）组成。 每个PMOS栅电极包括在该衬底上的第二硅化物区域（54）和在第二硅化物区域（54）上的第二金属区域（52）。 PMOS栅电极的第二硅化物区域（54）由具有接近硅的价带的功函数的第二硅化物（54）组成。

公开(公告)号：WO2004049445A1

公开(公告)日：2004-06-10

申请号：PCT/US2003/032782

申请日：2003-10-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KRIVOKAPIC, Zoran ,  AN, Judy, Xilin ,  LIN, Ming-Ren ,  WANG, Haihong

IPC: H01L27/088

CPC classification number: H01L27/1203 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/785 ,  H01L29/7856

Abstract: A NOR gate includes is constructed with two asymmetric FinFET type transistors (801, 802) instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.

Abstract translation: NOR门包括用两个非对称的FinFET型晶体管（801,802）代替传统的四晶体管或非门。 晶体管数量从四个减少到二个允许集成半导体电路的显着改进。