公开(公告)号：WO2003041150A3

公开(公告)日：2003-05-15

申请号：PCT/US2002/035832

申请日：2002-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WU, Yider ,  GHANDEHARI, Kouros ,  HUI, Angela ,  SHIELDS, Jeffrey, A. ,  CHANG, Kuo-Tung ,  LI, Wenmei ,  CHANG, Mark, S.

IPC: H01L21/311

Abstract: A method for removing a hard mask (26') during a semiconductor fabrication process is disclosed in which a hard mask (26') material is used to pattern a first material (20). The method includes a two-step removal process that includes performing a major wet etch to remove a majority of the hard mask (26') material, followed by performing a minor dry etch that removes a remainder of the hard mask (26') material.

公开(公告)号：WO1996012297A2

公开(公告)日：1996-04-25

申请号：PCT/US1995012194

申请日：1995-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HUANG, Richard, J. ,  HUI, Angela ,  CHEUNG, Robin ,  CHANG, Mark ,  LIN, Ming-Ren

IPC: H01L21/768

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. An embodiment comprises the simultaneous formation of a via and trench in a single etching step.

Abstract translation: 使用改进的双镶嵌工艺来制造包含具有减小的布线连接间隙的互连结构的半导体器件。 一个实施例是在单个蚀刻步骤中同时产生通孔和沟槽。

公开(公告)号：WO2003001601A2

公开(公告)日：2003-01-03

申请号：PCT/US2001/048825

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  DERHACOBIAN, Narbeh ,  WANG, Janet ,  HUI, Angela ,  PHAM, Tuan ,  SUNKAVALLI, Ravi ,  RANDOLPH, Mark

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a method of forming spacers (56) in a SONOS type nonvolatile semiconductor memory device, involving providing a substrate (40) having a core region (42) and periphery region (44), the core region (42) containing SONOS type memory cells (48) and the periphery region (44) containing gate transistors (50); implanting a first implant into the core region (42) and a first implant into the perifery region (44) of the substrate (40); forming a spacer material (52) over the substrate (40); masking the core region (42) and forming spacers (56) adjacent the gate transistors (50) in the perifery region (44); and implanting a second implant into the perifery region (44) of the substrate (40).

Abstract translation: 本发明的一个方面涉及一种在SONOS型非易失性半导体存储器件中形成间隔物（56）的方法，包括提供具有芯区（42）和周边区（44）的基底（40），芯区（ 42），包含SONOS型存储单元（48）和包含栅极晶体管（50）的外围区域（44）; 将第一植入物植入所述芯区域（42）中并将第一植入物植入所述基底（40）的所述外围区域（44）中; 在衬底（40）上形成间隔物（52）; 掩蔽所述芯区域（42）并在所述外形区域（44）中形成与所述栅极晶体管（50）相邻的间隔物（56）。 以及将第二植入物植入到所述基底（40）的外围区域（44）中。

公开(公告)号：EP1064679A1

公开(公告)日：2001-01-03

申请号：EP98963265.8

申请日：1998-12-17

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED ,  Fujitsu AMD Semiconductor Limited

Inventor： CHEN, Hung-Sheng ,  KIM, Unsoon ,  SUN, Yu ,  CHANG, Chi ,  RAMSBEY, Mark ,  RANDOLPH, Mark ,  KAJITA, Tatsuya ,  HUI, Angela ,  WANG, Fei ,  CHANG, Mark

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

公开(公告)号：EP0761014B1

公开(公告)日：2003-07-09

申请号：EP95935091.9

申请日：1995-09-25

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HUANG, Richard, J. ,  HUI, Angela ,  CHEUNG, Robin ,  CHANG, Mark ,  LIN, Ming-Ren

IPC: H01L21/768

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. An embodiment comprises the simultaneous formation of a via and trench in a single etching step.

公开(公告)号：EP0761014A1

公开(公告)日：1997-03-12

申请号：EP95935091.0

申请日：1995-09-25

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HUANG, Richard, J. ,  HUI, Angela ,  CHEUNG, Robin ,  CHANG, Mark ,  LIN, Ming-Ren

IPC: H01L21

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. An embodiment comprises the simultaneous formation of a via and trench in a single etching step.