公开(公告)号：WO1998010464A1

公开(公告)日：1998-03-12

申请号：PCT/US1997004986

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAO, Ming-Yin ,  OGLE, Robert, B., Jr. ,  WRISTERS, Derick

IPC: H01L21/28

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract translation: 描述了用于生长用作MOSFET栅极氧化物或用于EEPROM的隧道氧化物的超薄介电层的工艺。 通过一氧化氮和一氧化二氮气体中的一系列退火形成氮氧化物层，其在晶圆 - 氧氮化物界面处和氧氮化物表面处的氮浓度具有峰值，并且在氮氧化物本体中具有低氮浓度。 该方法提供精确的厚度控制，改进的界面结构，电子陷阱的低密度，并阻止从介质和衬底扩散掺杂剂杂质。 该过程很容易集成到现有的制造过程中，并且增加了很少的成本。

公开(公告)号：EP0928497A1

公开(公告)日：1999-07-14

申请号：EP97917648.0

申请日：1997-03-25

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HAO, Ming-Yin ,  OGLE, Robert, B., Jr. ,  WRISTERS, Derick

IPC: H01L21 ,  H01L27 ,  H01L29

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.