公开(公告)号：EP1264342A1

公开(公告)日：2002-12-11

申请号：EP01916603.2

申请日：2001-03-12

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SHIELDS, Jeffrey, A. ,  PHAM, Tuan, D. ,  RAMSBEY, Mark, T. ,  SUN, Yu ,  HUI, Angela, T. ,  CHAN, Maria, Chow

IPC: H01L21/8247 ,  H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/11526 ,  H01L27/11531

Abstract: In a two-step spacer fabrication process for a non-volatile memory device (1), a thin oxide layer (12) is deposited on a wafer substrate (3) leaving a gap in the core (24) of the non-volatile memory device (1). Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer (13) is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.

Abstract translation: 在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。 可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。 植入后，沉积第二间隔物。 在第二间隔物沉积之后，执行外围间隔物蚀刻。 通过上述方法，形成间隔物。

公开(公告)号：EP1060510B1

公开(公告)日：2008-10-22

申请号：EP99911155.2

申请日：1999-03-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： YU, Sun ,  PHAM, Tuan, D. ,  RAMSBEY, Mark, S. ,  CHANG, Chi

IPC: H01L21/762 ,  H01L21/8239

CPC classification number: H01L21/76221 ,  H01L27/105

Abstract: A method of providing thick and thin oxide structures (142, 146) reduces step changes between a core region (108) and a peripheral region (109) on an integrated circuit (112). Thin LOCOS structures (146) are provided in a core region (108) and a peripheral region (109) on an integrated circuit (112). Thin LOCOS structures (146, 148) are provided in a core region (108) of a flash memory device, and thick LOCOS structures (142, 144) are provided in a peripheral region (109) of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers (118, 160).

公开(公告)号：EP1060510A1

公开(公告)日：2000-12-20

申请号：EP99911155.2

申请日：1999-03-05

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： YU, Sun ,  PHAM, Tuan, D. ,  RAMSBEY, Mark, S. ,  CHANG, Chi

IPC: H01L21/762 ,  H01L21/8239

CPC classification number: H01L21/76221 ,  H01L27/105

Abstract: A method of providing thick and thin oxide structures (142, 146) reduces step changes between a core region (108) and a peripheral region (109) on an integrated circuit (112). Thin LOCOS structures (146) are provided in a core region (108) and a peripheral region (109) on an integrated circuit (112). Thin LOCOS structures (146, 148) are provided in a core region (108) of a flash memory device, and thick LOCOS structures (142, 144) are provided in a peripheral region (109) of the flash memory device. The device and process are not as susceptible to 'race track' problems, 'oxide' bump problems, and 'stringer' problems. The process utilizes two separate nitride or hard mask layers (118, 160).

公开(公告)号：EP1042804A1

公开(公告)日：2000-10-11

申请号：EP98964141.0

申请日：1998-12-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PHAM, Tuan, D. ,  HUI, Angela, T. ,  SAHOTA, Kashmir

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76237

Abstract: A method and system for providing a shallow trench isolation structure profile on a semiconductor is disclosed. The method and system includes patterning a mask on the semiconductor substrate, etching the mask such that the mask has sloped sides, etching the semiconductor substrate to form a trench whereby the trench has tapered sides, and planarizing the semiconductor substrate to optimize the trench depth and the width of the trench opening for subsequent processes. According to the method and system disclosed herein, the present invention allows a shallow trench isolation structure profile to be formed which has tapered sides.