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    MEMORY WORDLINE HARD MASK EXTENSION
    4.
    发明申请
    MEMORY WORDLINE HARD MASK EXTENSION 审中-公开

    公开(公告)号：WO2003083916A1

    公开(公告)日：2003-10-09

    申请号：PCT/US2003/001851

    申请日：2003-01-21

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： KAMAL, Tazrien ,  NGO, Minh, Van ,  RAMSBEY, Mark, T. ,  SHIELDS, Jeffrey, A. ,  YANG, Jean, Y. ,  LINGUNIS, Emmanuil ,  SHIRAIWA, Hidehiko ,  HUI, Angela, T.

    IPC: H01L21/28

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines (525) (526) formed by using the hard mask extensions (524). A charge-trapping dielectric material (504) is deposited over a semiconductor substrate (501) and first and second bitlines (512) are formed therein. A wordline material (515) and a hard mask material (515) are deposited over the wordline material (515). A photoresist material (518) is deposited over the hard mask material (515) and is processed to form a patterned photoresist material (518). The hard mask material (515) is processed using the patterned photoresist material (518) to form a patterned hard mask material (519). The patterned photoresist is then removed. A hard mask extension material (524) is deposited over the wordline material (515) and is processed to form a hard mask extension (524). The wordline material (515) is processed using the patterned hard mask material (519) and the hard mask extension (524) to form a wordline (525), and the patterned hard mask material (519) and the hard mask extension (524) are then removed.

    Abstract translation: 提供一种用于通过使用硬掩模延伸部（524）形成的具有紧密间隔的字线（525）（526）的集成电路存储器的制造方法。 电荷俘获电介质材料（504）沉积在半导体衬底（501）上，并且在其中形成第一和第二位线（512）。 字线材料（515）和硬掩模材料（515）沉积在字线材料（515）上。 光致抗蚀剂材料（518）沉积在硬掩模材料（515）上并被处理以形成图案化的光致抗蚀剂材料（518）。 使用图案化的光致抗蚀剂材料（518）处理硬掩模材料（515）以形成图案化的硬掩模材料（519）。 然后去除图案化的光致抗蚀剂。 硬掩模延伸材料（524）沉积在字线材料（515）上并被处理以形成硬掩模延伸部（524）。 使用图案化的硬掩模材料（519）和硬掩模延伸部（524）来加工字线材料（515）以形成字线（525），并且图案化的硬掩模材料（519）和硬掩模延伸部（524） 然后被删除。

    PROCESS FOR FORMING SUB-LITHOGRAPHIC PHOTORESIST FEATURES
    5.
    发明申请
    PROCESS FOR FORMING SUB-LITHOGRAPHIC PHOTORESIST FEATURES 审中-公开

    公开(公告)号：WO2002080239A3

    公开(公告)日：2002-10-10

    申请号：PCT/US2001/048509

    申请日：2001-12-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： SHIELDS, Jeffrey, A. ,  OKOROANYANWU, Uzodinma ,  YANG, Chih-Yuh

    IPC: H01L21/027

    Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer (16) after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer (16) has different etch rates in the vertical and horizontal directions. The modified photoresist layer (16) is trimmed with a plasma etch. A feature (54) included in the trimmed photoresist layer (16) has a sub-lithographic lateral dimension.

    A DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES
    6.
    发明公开
    A DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES 审中-公开
    EIN DUALABSTANDSHALTERVERFAHRENFÜRNICHT-FLÜCHTIGESPEICHERBAUELEMENTE

    公开(公告)号：EP1264342A1

    公开(公告)日：2002-12-11

    申请号：EP01916603.2

    申请日：2001-03-12

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： SHIELDS, Jeffrey, A. ,  PHAM, Tuan, D. ,  RAMSBEY, Mark, T. ,  SUN, Yu ,  HUI, Angela, T. ,  CHAN, Maria, Chow

    IPC: H01L21/8247 ,  H01L21/8246

    CPC classification number: H01L27/11568 ,  H01L27/11526 ,  H01L27/11531

    Abstract: In a two-step spacer fabrication process for a non-volatile memory device (1), a thin oxide layer (12) is deposited on a wafer substrate (3) leaving a gap in the core (24) of the non-volatile memory device (1). Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer (13) is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.

    Abstract translation: 在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。 可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。 植入后，沉积第二间隔物。 在第二间隔物沉积之后，执行外围间隔物蚀刻。 通过上述方法，形成间隔物。

    FABRICATING A HIGH COUPLING FLASH CELL
    8.
    发明公开
    FABRICATING A HIGH COUPLING FLASH CELL 有权
    研制高耦合快闪单元的

    公开(公告)号：EP1269537A1

    公开(公告)日：2003-01-02

    申请号：EP01914573.9

    申请日：2001-02-27

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： WANG, Larry, Yu ,  AVANZINO, Steven, C. ,  SHIELDS, Jeffrey, A. ,  PARK, Stephen, Keetai

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer (10) on a silicon substrate (12), forming an oxide (14) on the isolation formation layer (10), growing a tunnel oxide layer (16) thereon, depositing a first poly silicon layer (18), masking and etching the first poly silicon layer (18), depositing a second poly silicon layer (22) and performing a blanket etch back step, forming an oxide/nitride/oxide layer (26) forming a third poly-silicon layer (28) and depositing a silicide layer (30) thereon.

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