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    METHOD FOR FORMING CO-PLANAR CONDUCTOR AND INSULATOR FEATURES USING CHEMICAL MECHANICAL PLANARIZATION
    2.
    发明申请
    METHOD FOR FORMING CO-PLANAR CONDUCTOR AND INSULATOR FEATURES USING CHEMICAL MECHANICAL PLANARIZATION 审中-公开
    使用化学机械平面化形成共平面导体和绝缘体特征的方法

    公开(公告)号：WO1997048132A1

    公开(公告)日：1997-12-18

    申请号：PCT/US1997001714

    申请日：1997-02-11

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  SAHOTA, Kashmir, S. ,  VENKATKRISHNAN, Subramanian

    IPC: H01L21/768

    CPC classification number: H01L21/7684

    Abstract: A method is provided for forming conducting interconnects embedded in a layer of dielectric (38) such as an interlevel dielectric layer which resides over an integrated circuit structure (10). The conducting interconnects (38) and the layer of dielectric (40) may comprise, for example, metal and oxide, respectively. A CMP process which polishes both the interconnect material (i.e., the metal) and the dielectric (i.e., the oxide) at the same rate both locally and globally is employed to simultaneously polish the conducting interconnects (38) and the layer of dielectric (40). The CMP process effectively combines two CMP processing steps into one. Thus, the method of the present invention advantageously reduces the cost of manufacturing. Additionally, since both the layer of dielectric (40) and the conducting interconnects (38) are planarized in a single polishing step which polishes the interconnect material and the dielectric (e.g., metal and oxide) at rates which are essentially the same, the surface of the conducting interconnects (44) is level or co-planar with the surface of the layer of dielectric (46). The method of the present invention can be repeated to build multiple levels of conducting interconnects (38).

    Abstract translation: 提供了一种用于形成嵌入电介质层（38）的导电互连的方法，例如位于集成电路结构（10）上的层间电介质层。 导电互连（38）和电介质层（40）可以分别包括例如金属和氧化物。 采用以局部和全局以相同速率抛光互连材料（即，金属）和电介质（即，氧化物）的CMP工艺来同时抛光导电互连（38）和电介质层（40） ）。 CMP工艺有效地将两个CMP处理步骤组合成一个。 因此，本发明的方法有利地降低了制造成本。 另外，由于电介质层（40）和导电互连（38）都在单个研磨步骤中被平坦化，所述抛光步骤以基本上相同的速率抛光互连材料和电介质（例如，金属和氧化物），表面 的导电互连（44）与电介质层（46）的表面平齐或共面。 可以重复本发明的方法来构建多级导电互连（38）。

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