公开(公告)号：EP1420258A4

公开(公告)日：2005-01-12

申请号：EP02760692

申请日：2002-08-22

Applicant: ADVANTEST CORP

Inventor： SAKURAI RYUICHI ,  KASAHARA TOSHIHARU ,  SAITOH CHIEZOH

IPC: G01R31/28 ,  G01R31/319

CPC classification number: G01R31/31919 ,  G01R31/28

Abstract: Noise in measurement data received/transmitted from/to a measurement module is reduced. A measurement control unit 10 controls circuits 50a, b to be measured and acquires measurement data from the circuits 50a, b to be measured. Moreover, a CPU 20 controls the measurement control unit 10 via a bus 40. Since the CPU 20 does not directly control the circuits 50a, b to be controlled, no data is passed between the CPU 20 and the measurement control unit 10. Accordingly, a control signal and the like transmitted by the bus 40 is not mixed in the measurement data and the control signal and the like transmitted from the CPU 20 does not become a noise, thereby reducing the noise in the measurement data.

公开(公告)号：JPH0764729A

公开(公告)日：1995-03-10

申请号：JP23244893

申请日：1993-08-25

Applicant: ADVANTEST CORP

Inventor： ABIKO NORIHIDE ,  SAKURAI RYUICHI

IPC: G06F3/05

Abstract: PURPOSE:To provide the sample holding circuit which can prevent completely fetch missing of sampling data, in a measuring circuit for obtaining vector information by sampling an AC waveform at a prescribed interval, in a network analyzer, etc., of an electronic measuring technical field. CONSTITUTION:This sample holding circuit is constituted of a sample holding circuit 1 for sample-holding an analog signal, an A/D converter 2 for converting the analog signal subjected to sample holding to a digital signal, a counter 3 for executing a periodical count in synchronism with a control signal of a frequency of plural folds of the analog signal, for opening/closing control of a smaple switch of the sample holding circuit, a memory 4 for storing output data of the counter, and output data of plural A/D converters corresponding to a prescribed period of the analog signal in order to retain them temporarily, and a data processing system 5 for reading out the output data of the counter and the output data of the A/D converter, and fetching and processing them.

公开(公告)号：JP2003066099A

公开(公告)日：2003-03-05

申请号：JP2001253183

申请日：2001-08-23

Applicant: Advantest Corp ,  株式会社アドバンテスト

Inventor： SAKURAI RYUICHI ,  KASAHARA TOSHIHARU ,  SAITOU CHIEZOU

IPC: G01R31/28 ,  G01R31/319

CPC classification number: G01R31/31919 ,  G01R31/28

Abstract: PROBLEM TO BE SOLVED: To reduce noise of measurement data exchanged by a measurement module.
SOLUTION: A measurement control part 10 controls circuits 50a and b to be measured, and it acquires measurement data from the circuits 50a and b to be measured. A CPU 20 controls the measurement control part 10 via a bus 40. Since the CPU 20 does not directly control circuits 50a and b to be measured, no measurement data is exchanged between the CPU 20 and the measurement control part 10. Consequently, since a control signal or the like transmitted via the bus 40 is not mixed in the measurement data and the control signal or the like sent from the CPU 20 does not become noise, the noise of the measurement data is reduced.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：减少由测量模块交换的测量数据的噪声。 解决方案：测量控制部件10控制要测量的电路50a和b，并且从测量的电路50a和b获取测量数据。 CPU20经由总线40控制测量控制部分10.由于CPU 20不直接控制电路50a和b被测量，所以在CPU 20和测量控制部分10之间没有交换测量数据。因此，由于 经由总线40发送的控制信号等不在测量数据中混合，并且从CPU 20发送的控制信号等不会变得噪声，所以测量数据的噪声降低。

公开(公告)号：JPH0645937A

公开(公告)日：1994-02-18

申请号：JP19873792

申请日：1992-07-24

Applicant: ADVANTEST CORP

Inventor： SAKURAI RYUICHI ,  WAKAMOTO SATORU

IPC: H03M1/12 ,  G11C27/02

Abstract: PURPOSE:To inexpensively manufacture a rapid sample-and-hold circuit and an A/D converter by supplying a sampled/held output to an output terminal by a switch by a switch for switching an input synchronously with a reference clock signal. CONSTITUTION:The frequency of a reference clock to be supplied from the external to a reference clock input terminal 108 is set up to frequency 4f to be four times of signal frequency (f) inputted to a signal input terminal 101. A frequency dividing circuit 105 divides the frequency of the reference clock into 1/2 frequency and outputs the divided frequency to a sample-and-hold amplifier 102 and a phase shifter 104. The phase shifter 104 shifts the phase of the input signal by 2pi/2 and output the phase-shifted signal to a sample-and-hold amplifier 103. Respective amplifiers 102, 103 execute the sample-and-hold operation of an input signal to the terminal 101 based on the outputs of the circuit 105 and the phase shifter 104. Since the operation of the amplifiers 102, 103 is shifted at their periods by 2pi/2, a signal appearing on an output terminal 109 and the output of an A/D converter 107 become signals with the same period as a reference clock necessary for oversampling corresponding to twice of normal sampling.