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    CAPACITOR ARRANGEMENT AND A METHOD OF FORMING THE SAME
    1.
    发明申请
    CAPACITOR ARRANGEMENT AND A METHOD OF FORMING THE SAME 审中-公开
    电容器布置及其形成方法

    公开(公告)号：WO2011090440A1

    公开(公告)日：2011-07-28

    申请号：PCT/SG2011/000032

    申请日：2011-01-25

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  SINGH, Navab ,  KRIPESH, Vaidyanathan ,  LIM, Ying Ying ,  SOUNDARAPANDIAN, Mohanraj ,  AGARWAL, Ajay ,  NAGARAJAN, Ranganathan ,  SHI, Jinglin

    Inventor： SINGH, Navab ,  KRIPESH, Vaidyanathan ,  LIM, Ying Ying ,  SOUNDARAPANDIAN, Mohanraj ,  AGARWAL, Ajay ,  NAGARAJAN, Ranganathan ,  SHI, Jinglin

    IPC: H01L21/334 ,  H01G4/30

    CPC classification number: H01L27/0805 ,  H01G4/005 ,  H01G4/228 ,  H01G4/30 ,  H01L28/87 ,  H01L28/91

    Abstract: According to embodiments of the present invention, a capacitor arrangement is provided. The capacitor arrangement includes: a substrate; a first contact disposed over the substrate; a second contact disposed over the substrate; and a stack of layers, comprising: a plurality of first conductive layers; a plurality of second conductive layers; and a plurality of capacitive isolation layers; wherein the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers; and wherein the first conductive layers are electrically connected with the first contact and electrically isolated from the second contact and the second conductive layers are electrically connected with the second contact and electrically isolated from the first contact.

    Abstract translation: 根据本发明的实施例，提供一种电容器装置。 电容器布置包括：基板; 设置在所述基板上的第一触点; 设置在所述基板上的第二触点; 和一叠层，包括：多个第一导电层; 多个第二导电层; 和多个电容隔离层; 其中所述第一导电层，所述第二导电层和所述电容隔离层彼此交替，使得在两个相邻的第一导电层之间设置一个第二导电层，并且其中所述第一导电层和所述第二导电层与 彼此通过电容隔离层; 并且其中所述第一导电层与所述第一触点电连接并与所述第二触点电绝缘，并且所述第二导电层与所述第二触点电连接并与所述第一触点电隔离。

    DEVICE ARRANGEMENT
    2.
    发明申请
    DEVICE ARRANGEMENT 审中-公开
    设备安排

    公开(公告)号：WO2017065691A1

    公开(公告)日：2017-04-20

    申请号：PCT/SG2016/050492

    申请日：2016-10-06

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

    Inventor： SINGH, Navab ,  LEE, Jae Wung ,  MERUGU, Srinivas

    IPC: B81B7/02 ,  B81C1/00

    CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81B2203/0307 ,  B81B2207/015 ,  B81C1/00039 ,  B81C2203/0735

    Abstract: Various embodiments may provide a device arrangement. The device arrangement may include a substrate including a conductive layer. The device arrangement may further include a microelectromechanical systems (MEMS) device monolithically integrated with the substrate, wherein the MEMS device may be electrically coupled to the conductive layer. A cavity may be defined through the conductive layer for acoustically isolating the MEMS device from the substrate. At least one anchor structure may be defined by the conductive layer to support the MEMS device.

    Abstract translation: 各种实施例可以提供一种装置配置。 器件布置可以包括具有导电层的衬底。 器件布置可以进一步包括与衬底单片集成的微机电系统（MEMS）器件，其中MEMS器件可以电耦合到导电层。 可以通过导电层限定空腔，用于将MEMS器件与衬底声学隔离。 至少一个锚结构可以由导电层限定以支撑MEMS器件。

    A PIEZORESISTIVE SENSOR AND A METHOD OF CONTROLLING GIANT PIEZORESISTIVE COEFFICIENT OF AT LEAST ONE PIEZORESISTIVE ELEMENT
    3.
    发明申请
    A PIEZORESISTIVE SENSOR AND A METHOD OF CONTROLLING GIANT PIEZORESISTIVE COEFFICIENT OF AT LEAST ONE PIEZORESISTIVE ELEMENT 审中-公开
    一种PIEZORESISTIVE传感器和一种控制最小一个PIEZORESISTIVE元素的巨大PIEZORESISTIVE系数的方法

    公开(公告)号：WO2011005218A1

    公开(公告)日：2011-01-13

    申请号：PCT/SG2010/000255

    申请日：2010-07-06

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  NEUZIL, Pavel ,  WONG, Chee Chung ,  REBOUD, Julien ,  SHAO, Lichun ,  KOTLANKA, Rama Krishna ,  SINGH, Navab

    Inventor： NEUZIL, Pavel ,  WONG, Chee Chung ,  REBOUD, Julien ,  SHAO, Lichun ,  KOTLANKA, Rama Krishna ,  SINGH, Navab

    IPC: G01D5/16 ,  G01L9/06 ,  H01L41/04 ,  G01D21/00 ,  H01L27/20 ,  H01L41/083

    CPC classification number: G01L1/18

    Abstract: In an embodiment, a method of controlling giant piezoresistive coefficient of at least one piezoresistive element may be provided. The method may include providing an electric field to the at least one piezoresistive element to thereby create a depletion region in the at least one piezoresistive element; applying a stress onto the at least one piezoresistive element to modulate concentration and mobility of charge carriers along the at least one piezoresistive element; and varying the electric field applied onto the at least one piezoresistive element to control the giant piezoresistive coefficient of the at least one piezoresistive element. The application of stress alone may not change the giant piezoresistive coefficient, it may only change the resistance by changing the concentration and mobility of charge carriers. A piezoresistive sensor may also be provided.

    Abstract translation: 在一个实施例中，可以提供控制至少一个压阻元件的巨压阻系数的方法。 所述方法可以包括向所述至少一个压阻元件提供电场，从而在所述至少一个压阻元件中形成耗尽区; 在所述至少一个压阻元件上施加应力以调制沿所述至少一个压阻元件的载流子的浓度和迁移率; 并且改变施加到所述至少一个压阻元件上的电场以控制所述至少一个压阻元件的巨大的压阻系数。 单独施加应力可能不会改变巨型压阻系数，只能通过改变载流子的浓度和迁移率来改变电阻。 还可以提供压阻式传感器。

    A THROUGH SILICON INTERPOSER WAFER AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    A THROUGH SILICON INTERPOSER WAFER AND METHOD OF MANUFACTURING THE SAME 审中-公开
    一种通过硅插入晶片和制造该晶片的方法

    公开(公告)号：WO2017164816A8

    公开(公告)日：2017-09-28

    申请号：PCT/SG2017/050145

    申请日：2017-03-23

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

    Inventor： SINGH, Navab ,  CHEAM, Daw Don

    IPC: H01L23/48 ,  H01L23/52 ,  B81B7/00

    Abstract: A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.

    Abstract translation: 提供了一种贯穿硅中介层晶片，其具有至少一个形成在其中用于MEMS应用的腔体及其制造方法。 硅通孔插件晶片包括充分靠近至少一个空腔形成的一个或多个填充硅通孔，以在插件晶片的后续处理期间为至少一个空腔的壁提供支撑。

    THERMOELECTRIC DEVICE AND METHOD FOR MANUFACTURING A THERMOELECTRIC DEVICE
    7.
    发明申请
    THERMOELECTRIC DEVICE AND METHOD FOR MANUFACTURING A THERMOELECTRIC DEVICE 审中-公开
    热电装置及制造热电装置的方法

    公开(公告)号：WO2011162726A1

    公开(公告)日：2011-12-29

    申请号：PCT/SG2011/000223

    申请日：2011-06-23

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  BUDDHARAJU, Kavitha ,  LI, Yida ,  SINGH, Navab ,  LO, Guo Qiang Patrick

    Inventor： BUDDHARAJU, Kavitha ,  LI, Yida ,  SINGH, Navab ,  LO, Guo Qiang Patrick

    IPC: H01L35/14 ,  B82B1/00 ,  B82B3/00 ,  B82Y40/00 ,  H01L35/28 ,  H01L35/34

    CPC classification number: B82Y40/00 ,  B82Y10/00 ,  B82Y30/00 ,  H01L35/32 ,  H01L35/34

    Abstract: According to embodiments of the present invention, a thermoelectric device is provided. The thermoelectric device may include a plurality of cells, where each cell includes a first electrode including a first electrode portion and a second electrode portion; a first nanowire, wherein a first end of the first nanowire is coupled to the first electrode portion of the first electrode, the first nanowire being doped with doping atoms of a first conductivity type; and a second nanowire, wherein a first end of the second nanowire is coupled to the second electrode portion of the first electrode, the second nanowire being doped with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type; and wherein a second end of the first nanowire is coupled to a second electrode, the second electrode coupled to an adjacent cell; wherein a second end of the second nanowire is coupled to a further second electrode, the further second electrode coupled to a further adjacent cell; and wherein at least one of the first electrode and a portion at the second end of the first nanowire and the second end of the second nanowire are silicided.

    Abstract translation: 根据本发明的实施例，提供了一种热电装置。 热电装置可以包括多个单元，其中每个单元包括包括第一电极部分和第二电极部分的第一电极; 第一纳米线，其中第一纳米线的第一端耦合到第一电极的第一电极部分，第一纳米线掺杂有第一导电类型的掺杂原子; 和第二纳米线，其中第二纳米线的第一端耦合到第一电极的第二电极部分，第二纳米线掺杂有第二导电类型的掺杂原子，第二导电类型不同于第一导电类型 ; 并且其中所述第一纳米线的第二端耦合到第二电极，所述第二电极耦合到相邻电池; 其中所述第二纳米线的第二端耦合到另一第二电极，所述另外的第二电极耦合到另一相邻电池; 并且其中所述第一电极和所述第一纳米线的第二末端部分和所述第二纳米线的第二末端中的至少一个被硅化。

    A STACKED SILICON-GERMANIUM NANOWIRE STRUCTURE AND A METHOD OF FORMING THE SAME
    8.
    发明申请
    A STACKED SILICON-GERMANIUM NANOWIRE STRUCTURE AND A METHOD OF FORMING THE SAME 审中-公开
    堆叠硅 - 锗纳米结构及其形成方法

    公开(公告)号：WO2008069765A1

    公开(公告)日：2008-06-12

    申请号：PCT/SG2007/000423

    申请日：2007-12-07

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  LO, Guo Qiang ,  BERA, Lakshmi Kanta ,  NGUYEN, Hoai Son ,  SINGH, Navab

    Inventor： LO, Guo Qiang ,  BERA, Lakshmi Kanta ,  NGUYEN, Hoai Son ,  SINGH, Navab

    IPC: H01L21/336 ,  H01L21/20 ,  B82B3/00

    CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392

    Abstract: A method of forming a stacked silicon-germanium nanowire structure on a support substrate is disclosed. The method includes forming a stacked structure on the support substrate, the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer; forming a fin structure from the stacked structure, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing the fin portion of the fin structure thereby forming the silicon-germanium nanowire being surrounded by a layer of oxide; and removing the layer of oxide to form the silicon-germanium nanowire. A method of forming a gate-all-around transistor comprising forming a stacked silicon-germanium nanowire structure that has been formed on a support substrate is also disclosed. A stacked silicon-germanium nanowire structure and a gate-all-around transistor comprising the stacked silicon-germanium nanowire structure are also disclosed.

    Abstract translation: 公开了一种在支撑衬底上形成堆叠的硅 - 锗纳米线结构的方法。 该方法包括在支撑基板上形成堆叠结构，该堆叠结构包括至少一个沟道层和沉积在沟道层上的至少一个沟道间层; 从所述堆叠结构形成翅片结构，所述翅片结构包括至少两个支撑部分和布置在其间的翅片部分; 氧化翅片结构的翅片部分，从而形成被一层氧化物包围的硅 - 锗纳米线; 并去除氧化物层以形成硅 - 锗纳米线。 还公开了一种形成栅极全绕晶体管的方法，包括形成已经形成在支撑衬底上的堆叠的硅 - 锗纳米线结构。 还公开了堆叠的硅 - 锗纳米线结构和包括堆叠的硅 - 锗纳米线结构的栅极全绕晶体管。

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