公开(公告)号：WO0169837A9

公开(公告)日：2003-02-27

申请号：PCT/US0108159

申请日：2001-03-14

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02 ,  H04L7/033 ,  G06F1/04

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system.

Abstract translation: 可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行增强，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者其可以全部或部分地在单独的集成电路上。 电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 电路可以是较大系统的一部分。

公开(公告)号：WO0169837A3

公开(公告)日：2003-01-03

申请号：PCT/US0108159

申请日：2001-03-14

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02 ,  H04L7/033 ,  G06F1/04

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system.

Abstract translation: 可编程逻辑器件（“PLD”）增加了可编程时钟数据恢复（“CDR”）电路，以允许PLD通过任何大量的CDR信令协议进行通信。 CDR电路可以与PLD集成，或者其可以全部或部分位于单独的集成电路上。 该电路可以具有CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力（例如非CDR低压差分信令（“LVDS”））结合提供。 电路可能是更大系统的一部分。

公开(公告)号：DE60220300D1

公开(公告)日：2007-07-05

申请号：DE60220300

申请日：2002-08-05

Applicant: ALTERA CORP

Inventor： STARR GREG ,  AUNG EDWARD

IPC: G06F1/04 ,  G06F11/16 ,  G06F1/08 ,  H03K5/00 ,  H03K5/19 ,  H03K17/00 ,  H03L7/00 ,  H03L7/095 ,  H03L7/14 ,  H04L7/00

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

公开(公告)号：DE60220300T2

公开(公告)日：2008-01-17

申请号：DE60220300

申请日：2002-08-05

Applicant: ALTERA CORP

Inventor： STARR GREG ,  AUNG EDWARD

IPC: G06F1/04 ,  G06F11/16 ,  G06F1/08 ,  H03K5/00 ,  H03K5/19 ,  H03K17/00 ,  H03L7/00 ,  H03L7/095 ,  H03L7/14 ,  H04L7/00

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

公开(公告)号：DE60144544D1

公开(公告)日：2011-06-09

申请号：DE60144544

申请日：2001-03-14

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/02 ,  H04L7/04 ,  G06F1/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/033

公开(公告)号：DE60137324D1

公开(公告)日：2009-02-26

申请号：DE60137324

申请日：2001-03-14

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/02 ,  H04L7/04 ,  G06F1/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/033

Abstract: A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ('LVDS'). The circuitry may be part of a larger system.

公开(公告)号：AU2002326532A1

公开(公告)日：2003-02-17

申请号：AU2002326532

申请日：2002-08-05

Applicant: ALTERA CORP

Inventor： AUNG EDWARD ,  STARR GREG

IPC: G06F1/04 ,  G06F1/08 ,  H03K5/00 ,  H03K5/19 ,  H03K17/00 ,  H03L7/00 ,  H03L7/095 ,  H03L7/14 ,  H04L7/00 ,  G06F11/16

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

公开(公告)号：JP2013179659A

公开(公告)日：2013-09-09

申请号：JP2013095012

申请日：2013-04-30

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/033 ,  H04L7/04 ,  G11C7/22 ,  H03K5/00 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/183 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide a clock data recover circuit mounted on a programmable logic device or provided by being coupled to the programmable logic device.SOLUTION: A programmable logic device ("PLD") is equipped with a programmable clock data recovery ("CDR") circuit to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuit may be built in the PLD, or it may be wholly or partly on a separate integrated circuit. The circuit may be capable of CDR input, CDR output, or both. A CDR function may be provided in combination with other non-CDR signaling function such as non-CDR low voltage differential signaling ("LVDS"). The circuit may be part of a large system.

Abstract translation: 要解决的问题：提供安装在可编程逻辑器件上或通过耦合到可编程逻辑器件提供的时钟数据恢复电路。解决方案：可编程逻辑器件（“PLD”）配备有可编程时钟数据恢复（“ CDR“）电路以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以内置在PLD中，或者它可以全部或部分地在单独的集成电路上。 该电路可能能够进行CDR输入，CDR输出或两者兼容。 CDR功能可以与诸如非CDR低电压差分信令（“LVDS”）的其它非CDR信令功能组合提供。 该电路可能是大系统的一部分。

公开(公告)号：JP2007195254A

公开(公告)日：2007-08-02

申请号：JP2007105344

申请日：2007-04-12

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02 ,  H04L7/033

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide a clock data recovery circuit which is provided on a programmable logic device or coupled to the programmable logic device. SOLUTION: A programmable logic device ("PLD") includes a programmable clock data recover ("CDR") circuit in order to communicate with PLD by arbitrary one of a large number of CDR signaling protocols. The CDR circuit can be built in the PLD, or it can be made entirely or partially independent integrated circuit. The circuit can perform CDR input, CDR output, or those both. The CDR function can be provided, in combination with other non-CDR signaling function, such as non-CDR low voltage driving signaling ("LVDS"). The circuit can be a part of a large-scale system. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提供在可编程逻辑器件上或耦合到可编程逻辑器件的时钟数据恢复电路。 解决方案：可编程逻辑器件（“PLD”）包括可编程时钟数据恢复（“CDR”）电路，以便通过大量CDR信令协议中的任意一个与PLD进行通信。 CDR电路可以内置在PLD中，或者可以制成完全或部分独立的集成电路。 电路可以执行CDR输入，CDR输出或两者。 CDR功能可以与其他非CDR信令功能一起提供，例如非CDR低电压驱动信令（“LVDS”）。 该电路可以是大规模系统的一部分。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006262513A

公开(公告)日：2006-09-28

申请号：JP2006128713

申请日：2006-05-02

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02 ,  H04L7/033

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide a clock data recovery circuitry which is provided on a programmable logic device or is coupled with the programmable logic device. SOLUTION: A programmable logic device ("PLD") is installed with a programmable clock data recover ("CDR") circuitry to allow the PLD, to communicate via any of a large number of CDR signaling protocols. The CDR circuit may be integrated with the PLD, or it may be made wholly or partly on a separate integrated circuit. The circuit may be capable of CDR input, CDR output, or both. The CDR capability may be provided, in combination with other non-CDR signaling capability, such as non-CDR low voltage differential signaling ("LVDS"). The circuit may be a part of a large-scaled system. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种提供在可编程逻辑器件上或与可编程逻辑器件耦合的时钟数据恢复电路。 解决方案：可编程逻辑器件（“PLD”）安装有可编程时钟数据恢复（“CDR”）电路，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者它可以完全或部分地制成在单独的集成电路上。 该电路可能能够进行CDR输入，CDR输出或两者兼容。 CDR能力可以与其他非CDR信令能力相结合，例如非CDR低电压差分信令（“LVDS”）。 该电路可能是大规模系统的一部分。 版权所有（C）2006，JPO＆NCIPI