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    HIGH-SPEED SERIAL DATA RECEIVER ARCHITECTURE
    4.
    发明申请
    HIGH-SPEED SERIAL DATA RECEIVER ARCHITECTURE 审中-公开
    高速串行数据接收机架构

    公开(公告)号：WO2007019222A2

    公开(公告)日：2007-02-15

    申请号：PCT/US2006030248

    申请日：2006-08-02

    Applicant: ALTERA CORP ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY YURYEVICH ,  MAANGAT SIMARDEEP ,  WONG WILSON ,  PATEL RAKESH

    Inventor： TRAN THUNGOC M ,  SHUMARAYEV SERGEY YURYEVICH ,  MAANGAT SIMARDEEP ,  WONG WILSON ,  PATEL RAKESH

    IPC: H04L25/03

    CPC classification number: H04L1/243 ,  H04L25/03878

    Abstract: Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

    Abstract translation: 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

    INTERCONNECTION RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES
    5.
    发明申请
    INTERCONNECTION RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 审中-公开
    可编程逻辑集成电路设备的互连资源

    公开(公告)号：WO0052825A9

    公开(公告)日：2001-11-29

    申请号：PCT/US0005488

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

    IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES
    6.
    发明申请
    INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 审中-公开
    用于可编程逻辑集成电路设备的互连和输入/输出资源

    公开(公告)号：WO0052826A2

    公开(公告)日：2000-09-08

    申请号：PCT/US0005628

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

    Abstract: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    Abstract translation: 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    High-speed data receiving circuit network and method
    7.
    发明专利
    High-speed data receiving circuit network and method 有权
    高速数据接收电路和方法

    公开(公告)号：JP2007037114A

    公开(公告)日：2007-02-08

    申请号：JP2006187052

    申请日：2006-07-06

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY Y ,  WONG WILSON ,  PATEL RAKESH

    IPC: H04L25/03 ,  H04B3/06

    CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit network which compensates losses, such as decrease in signal amplitude and abrupt changes, in order to maintain accurate and high-speed data transmission.
    SOLUTION: An equalizing circuit network (10), receiving a digital data signal, includes both a feedforward equalizer (FFE)(30) and a determination feedback equalizer (DFE)(90). The FFE circuit network (30) is used for providing at least sufficient minimum signal to the DFE circuit network (90) and an adequate startup of the DFE circuit network (90). Accordingly, the heavier the load of an equalizing task is, the more the task can be shifted, from the FFE circuit network (30) to the DFE circuit network (90).
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供补偿诸如信号幅度和突然变化的损失的电路网络，以便保持精确和高速的数据传输。 解决方案：接收数字数据信号的均衡电路网络（10）包括前馈均衡器（FFE）（30）和确定反馈均衡器（DFE）（90）。 FFE电路网络（30）用于向DFE电路网络（90）提供至少足够的最小信号和DFE电路网络（90）的适当启动。 因此，平衡任务的负担越重，任务可以从FFE电路网络（30）到DFE电路网络（90）的移动越多。 版权所有（C）2007，JPO＆INPIT

    Interconnection and input/output resources for programmable logic integrated circuit devices
    8.
    发明专利
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    用于可编程逻辑集成电路设备的互连和输入/输出资源

    公开(公告)号：JP2006287964A

    公开(公告)日：2006-10-19

    申请号：JP2006146009

    申请日：2006-05-25

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

    IPC: H03K19/177 ,  H01L21/82 ,  H03K19/173

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources to be applied to a programmable logic device for accelerating an operating speed of a programmable logic array integrated circuit. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors) are provided for making programmable interconnection to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路的工作速度。 解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 互连资源（例如，互连导体）被提供用于对区域之间进行可编程的互连。 这些互连资源中的至少一些以架构上相似但具有显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2007，JPO＆INPIT

    PROGRAMMABLE LOGIC DEVICE WITH UNIFIED CELL STRUCTURE INCLUDING SIGNAL INTERFACE BUMPS
    9.
    发明专利
    PROGRAMMABLE LOGIC DEVICE WITH UNIFIED CELL STRUCTURE INCLUDING SIGNAL INTERFACE BUMPS 失效

    公开(公告)号：JP2001135728A

    公开(公告)日：2001-05-18

    申请号：JP2000250337

    申请日：2000-07-17

    Applicant: ALTERA CORP

    Inventor： SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH

    IPC: H01L27/04 ,  G06F7/38 ,  H01L21/82 ,  H01L21/822 ,  H01L25/00 ,  H01L27/118 ,  H05K7/02

    Abstract: PROBLEM TO BE SOLVED: To provide a standard cell element of which layout, wiring connection, manufacture and input/output connection architecture can be simplified in a programmable logic device, in which an increasing die size and a packaging density makes a signal path longer and finer, and as a result, presenting the problem of signal delay and signal skew. SOLUTION: A unified cell 80 comprises a cell 86 of a logic array block, a hexagonal interface bump 82 of which size can be easily changed, a trace 88 for electrically connecting a signal drive from an input/output band 84 to a bump 82, a separated power bus 90. The input/output band 84 is aligned with the input/output band 84 of a neighboring unified cell. This eliminates the need for a conventional connection circuit.

    Interconnection and input/output resources for programmable logic integrated circuit devices
    10.
    发明专利
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    用于可编程逻辑集成电路设备的互连和输入/输出资源

    公开(公告)号：JP2009065694A

    公开(公告)日：2009-03-26

    申请号：JP2008270378

    申请日：2008-10-20

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

    IPC: H03K19/173 ,  H01L21/82 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit (10) has a plurality of regions of programmable logic (20) disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, etc.) are provided for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms having architecturally similar but significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列的多个设备上。 提供互连资源（例如，互连导体等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以具有架构上相似但显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2009，JPO＆INPIT

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