公开(公告)号：WO2011146453A3

公开(公告)日：2012-01-12

申请号：PCT/US2011036773

申请日：2011-05-17

Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

Inventor： SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

IPC: H03K19/0175 ,  H03L7/08 ,  H04L25/02

CPC classification number: H03L7/0805 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/0891 ,  H03L7/095

Abstract: An integrated circuit includes physical media attachment ("PMA") circuitry that includes two different kinds of transceiver channels for serial data 5 signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively 10 usable as phase-locked loop ("PLL") circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract translation: 集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据5信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可选地10可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。 低速通道也可以从单独的低速PLL电路获取时钟信号。

公开(公告)号：EP2572453A4

公开(公告)日：2016-03-02

申请号：EP11784073

申请日：2011-05-17

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

IPC: H03K19/0175 ,  H03K19/177 ,  H03L7/08 ,  H04L25/02

CPC classification number: H03L7/0805 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/0891 ,  H03L7/095

Abstract: An integrated circuit includes physical media attachment (PMA) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (PLL) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.