公开(公告)号：WO2011146453A3

公开(公告)日：2012-01-12

申请号：PCT/US2011036773

申请日：2011-05-17

Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

Inventor： SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

IPC: H03K19/0175 ,  H03L7/08 ,  H04L25/02

CPC classification number: H03L7/0805 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/0891 ,  H03L7/095

Abstract: An integrated circuit includes physical media attachment ("PMA") circuitry that includes two different kinds of transceiver channels for serial data 5 signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively 10 usable as phase-locked loop ("PLL") circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract translation: 集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据5信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可选地10可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。 低速通道也可以从单独的低速PLL电路获取时钟信号。

公开(公告)号：WO2011133565A2

公开(公告)日：2011-10-27

申请号：PCT/US2011033071

申请日：2011-04-19

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

IPC: G06F9/455 ,  G06F11/25 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two- dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括诸如传递函数，概率密度函数和眼睛特征的特征函数。 链接仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：WO2010042447A3

公开(公告)日：2010-07-22

申请号：PCT/US2009059569

申请日：2009-10-05

Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ATESOGLU ALI

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ATESOGLU ALI

IPC: H03B5/08 ,  H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

Abstract: An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Abstract translation: 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和可选导体。 选择导体形成晶体管中的一个与电容器或变容二极管之间的至少一部分连接。

公开(公告)号：AT466409T

公开(公告)日：2010-05-15

申请号：AT06000671

申请日：2000-07-14

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH

IPC: H01L27/04 ,  H03K19/177 ,  G06F7/38 ,  H01L21/82 ,  H01L21/822 ,  H01L25/00 ,  H01L27/02 ,  H01L27/118 ,  H05K3/40 ,  H05K7/02

Abstract: A programmable logic device package comprising: a package (64); a solder ball (66) positioned on a first surface of said package, said solder ball located for receiving an external signal, a plurality of signal interface bumps (62) positioned on a second surface of the package, and a set of routing leads (68) extending through said package and connecting said solder ball to each of the plurality of signal interface bumps, wherein said set of routing leads distribute said external signal to said signal interface bumps.

公开(公告)号：WO2012021332A3

公开(公告)日：2012-04-12

申请号：PCT/US2011046239

申请日：2011-08-02

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  SHUMARAYEV SERGEY ,  DING WEIQI ,  NARAYAN SRIRAM ,  CHOW DANIEL TUN LAI ,  PAN MINGDE

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  SHUMARAYEV SERGEY ,  DING WEIQI ,  NARAYAN SRIRAM ,  CHOW DANIEL TUN LAI ,  PAN MINGDE

IPC: G01R31/303

CPC classification number: G01R31/31709 ,  G01R31/3171 ,  G01R31/31716 ,  H04L7/0337

Abstract: An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

公开(公告)号：WO2011119369A3

公开(公告)日：2011-11-24

申请号：PCT/US2011028465

申请日：2011-03-15

Applicant: ALTERA CORP ,  DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  ATESOGLU ALI ,  IPPILI SHARAT BABU

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  ATESOGLU ALI ,  IPPILI SHARAT BABU

IPC: H03L7/099 ,  H01F17/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively coupled to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be coupled to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor air in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract translation: 提供带锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，电压控制振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲器电路。 多个电感器中的选定的一个可以被主动地耦合到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以耦合到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲器电路中的相应输入晶体管空气。 通过向振荡器电路中选定的一个提供高电压，并通过向其余振荡器电路提供地电压，在正常操作期间，可以选择一个振荡器电路。

公开(公告)号：WO2010135097A2

公开(公告)日：2010-11-25

申请号：PCT/US2010034149

申请日：2010-05-08

Applicant: ALTERA CORP ,  HOANG TIM TRI ,  TRAN THUNGOC ,  WONG WILSON ,  SHUMARAYEV SERGEY

Inventor： HOANG TIM TRI ,  TRAN THUNGOC ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: G06F1/10 ,  H03K19/177

CPC classification number: G06F1/10

Abstract: A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.

Abstract translation: 电路包括第一区域，第二区域和第三区域。 第二区域包括产生时钟信号的锁定环路电路。 锁定环电路接收与第一区域中产生的噪声隔离的电源电压。 第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。 第三个区域与电路中的第二个区域分开。

公开(公告)号：WO2010039232A2

公开(公告)日：2010-04-08

申请号：PCT/US2009005396

申请日：2009-09-29

Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  WONG WILSON

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON

IPC: H04L27/01

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L1/205 ,  H04L25/03019

Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

Abstract translation: 用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。 均衡器电路可以包括可控可变DC增益和可控可变AC增益。 该电路还可以包括用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号的眼高和眼宽度监视器电路。 第一输出信号可以用于控制均衡器电路的DC增益，第二输出信号可以用于控制均衡器电路的AC增益。

公开(公告)号：WO2009126267A3

公开(公告)日：2010-01-14

申请号：PCT/US2009002188

申请日：2009-04-07

Applicant: ALTERA CORP ,  CHAN ALLEN ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  DING WEIQI

Inventor： CHAN ALLEN ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  DING WEIQI

IPC: H04L12/56

CPC classification number: H04L49/30 ,  H04L49/352

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

Abstract translation: 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10吉比特以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US6281704B2

公开(公告)日：2001-08-28

申请号：US81011601

申请日：2001-03-15

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  CHEUNG SAMMY ,  PATEL RAKESH ,  CHAN VINSON

IPC: H01L23/522 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H01L23/5222 ,  H01L2924/0002 ,  H03K19/1778 ,  H03K19/17792 ,  H03K19/17796 ,  H01L2924/00

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.