公开(公告)号：GB2326502B

公开(公告)日：2000-11-29

申请号：GB9813341

申请日：1998-06-19

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS ,  LANE CHRISTOPHER F

IPC: H03K19/173 ,  H03K19/177

Abstract: An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer. A second-level multiplexer connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about +E,fra 1/3+EE .

公开(公告)号：GB2318663A

公开(公告)日：1998-04-29

申请号：GB9718147

申请日：1997-08-27

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS ,  MEJIA MANUEL

IPC: H03K19/177

Abstract: A hierarchical interconnect structure between logic elements LE, logic array blocks and global interconnects in a programmable logic device provides a first group 104 of local interconnect lines that couple to outputs of more than one logic element in a block, and a second group 106 of local interconnect lines that are divided into independent segments coupled to a subset of the logic elements in a block. By eliminating the one-to-one correspondence between the number of logic elements in a logic array block and the number of local interconnect wires, the present invention makes possible the inclusion of more logic elements in one block in an area efficient manner.

公开(公告)号：GB2318663B

公开(公告)日：2000-06-28

申请号：GB9718147

申请日：1997-08-27

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS ,  MEJIA MANUEL

IPC: H03K19/177

公开(公告)号：GB2326502A

公开(公告)日：1998-12-23

申请号：GB9813341

申请日：1998-06-19

Applicant: ALTERA CORP

Inventor： REDDY SRINIVAS ,  LANE CHRISTOPHER F

IPC: H03K19/173 ,  H03K19/177

Abstract: In a multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs, a single connection e.g. 312 connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer 310. A second-level multiplexer 306 or 306' connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about 1/3. In other embodiments, each second-level multiplexer has four (rather than two) inputs, achieved by doubling the number of first-level multiplexers 310 or having each feed two second-level multiplexers on each side.

公开(公告)号：JP2007081426A

公开(公告)日：2007-03-29

申请号：JP2006320925

申请日：2006-11-28

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture which allows an IP functional block to be arranged to optimize the routing architecture of base signals. SOLUTION: This programmable logical device (PLD) is provided with a plurality of logical elements(LEs) constituted into an array and the routing architecture of the base signals provided with a plurality of signal routing lines for routing signals among the LEs. A hole is formed inside the array of the LEs, the hole is featured by a peripheral part and a center part, the routing architecture of the base signals is at least partially interrupted at the hole, and the PLD is further provided with an interface circuit inside the peripheral part of the hole. The interface circuit can be constituted so that a circuit inside the hole is coupled to the architecture of routing the signals, and the PLD is further provided with the IP functional block inside the hole and is electrically coupled to the interface circuit. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种PLD架构，其允许IP功能块被布置成优化基本信号的路由架构。 解决方案：该可编程逻辑器件（PLD）被提供有构成阵列的多个逻辑元件（LE），并且基准信号的路由架构设置有用于在LE之间路由信号的多个信号路由线。 在LE的阵列内部形成一个孔，孔由周边部分和中心部分组成，基本信号的路由结构在孔处至少部分中断，并且PLD还具有接口电路 在孔的周边部分内。 接口电路可以构成为使得孔内的电路耦合到路由信号的架构，并且PLD还在孔内设置有IP功能块，并且电耦合到接口电路。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005229650A

公开(公告)日：2005-08-25

申请号：JP2005121750

申请日：2005-04-19

Applicant: Altera Corp ,  アルテラ・コーポレーション

Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture capable of arranging an IP functional block so as to optimize the routing architecture of a base signal. SOLUTION: A programmable logic device (PLD) is provided with a plurality of logical elements (LE) constituted into an array and the routing architecture of the base signal provided with a plurality of signal-routing lines for routing signals among the LEs. A hole is formed inside the array of the LEs, the hole is featured by a peripheral part and a center part and the routing architecture of the base signal is at least partially interrupted at the hole. The PLD is further provided with an interface circuit inside the peripheral part of the hole, and the interface circuit can be constituted so as to connect a circuit inside the hole to the architecture of routing the signal. The PLD is provided with the IP functional block inside the hole further and is electrically connected to the interface circuit. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够布置IP功能块以便优化基本信号的路由架构的PLD架构。 解决方案：可编程逻辑器件（PLD）被提供有构成阵列的多个逻辑元件（LE），并且基本信号的路由架构具有多个信号路由线，用于在LE之间路由信号 。 在LE的阵列内部形成一个孔，孔由外围部分和中心部分组成，基部信号的路由结构在孔处至少部分中断。 PLD还在孔的周边部分内设置有接口电路，并且接口电路可以构成为将孔内的电路连接到路由信号的架构。 PLD还在孔内部设置有IP功能块，并且电连接到接口电路。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2011066437A

公开(公告)日：2011-03-31

申请号：JP2010247959

申请日：2010-11-04

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture capable of arranging an IP function block so as to optimize a routing architecture of a base signal. SOLUTION: A programmable logic device (PLD) has: two or more logic elements (LE) configured into an array; and a routing architecture of a base signal provided with a plurality of signal rooting lines for rooting signals between LEs. A hole is formed in the LE array. The hole is characterized by a peripheral part and a central part. The routing architecture of the base signal is at least partially interrupted in the hole. The PLD further has an interface circuit at the periphery part of the hole. The interface circuit can be configured in such a way that the circuit in the hole is combined with architecture in which signals are subjected to routing. The PLD further has an IP function block in the hole and is electrically connected with the interface circuit. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供能够布置IP功能块以便优化基本信号的路由架构的PLD架构。 解决方案：可编程逻辑器件（PLD）具有：将两个或多个逻辑元件（LE）配置为阵列; 以及设置有用于在LE之间生成信号的多个信号生根线的基本信号的路由架构。 在LE阵列中形成一个孔。 该孔的特征在于周边部分和中心部分。 基座信号的路由架构在孔中至少部分中断。 PLD还在孔的周边部分具有接口电路。 接口电路可以被配置成使得孔中的电路与信号经过路由的架构相结合。 PLD还在孔中具有IP功能块，并与接口电路电连接。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2003023083A

公开(公告)日：2003-01-24

申请号：JP2002118440

申请日：2002-04-19

Applicant: Altera Corp ,  アルテラ・コーポレーション

Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture capable of arranging an IP functional block so as to optimize the routing architecture of base signals. SOLUTION: The programmable logical device(PLD) is provided with a plurality of logical elements(LEs) constituted into an array and the routing architecture of the base signals provided with a plurality of signal-routing lines for routing signals among the LEs. A hole is formed inside the array of the LEs, the hole is featured by a peripheral part and a center part and the routing architecture of the base signals is at least partially interrupted at the hole. The PLD is further provided with an interface circuit inside the peripheral part of the hole and the interface circuit can be constituted so as to connect a circuit inside the hole to the architecture of routing the signals. The PLD is provided with the IP functional block inside the hole further and is electrically connected to the interface circuit.

Abstract translation: 要解决的问题：提供能够布置IP功能块以便优化基本信号的路由架构的PLD架构。 解决方案：可编程逻辑器件（PLD）设置有构成阵列的多个逻辑元件（LE），并且基带信号的路由架构具有用于在LE之间路由信号的多条信号路由线路。 在LE的阵列内部形成一个孔，孔由周边部分和中心部分组成，基部信号的路由结构在孔处至少部分中断。 PLD还在孔的周边部分内设置有接口电路，并且接口电路可以构成为将孔内的电路连接到路由信号的架构。 PLD还在孔内部设置有IP功能块，并且电连接到接口电路。