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14 records (took 0.02 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE69925982T2

    公开(公告)日：2006-05-04

    申请号：DE69925982

    申请日：1999-11-26

    Applicant: ALTERA CORP

    Inventor： MEJIA MANUEL

    IPC: G06F3/00 ,  H03K19/0185 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003

    Abstract: A circuit includes an output node, a set of output transistors operative to control the signal level on the output node, a first voltage supply, and a second voltage supply. A hot socket detection circuit identifies when the first voltage supply or the second voltage supply is below a predetermined value indicative of a hot socket condition. In response to a hot socket condition, the hot socket detection circuit generates control signals that place the set of output transistors in a high impedance state.

    3.
    发明专利
    未知

    公开(公告)号：AT298948T

    公开(公告)日：2005-07-15

    申请号：AT99309462

    申请日：1999-11-26

    Applicant: ALTERA CORP

    Inventor： MEJIA MANUEL

    IPC: G06F3/00 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003 ,  H03K19/0185

    Abstract: A circuit includes an output node, a set of output transistors operative to control the signal level on the output node, a first voltage supply, and a second voltage supply. A hot socket detection circuit identifies when the first voltage supply or the second voltage supply is below a predetermined value indicative of a hot socket condition. In response to a hot socket condition, the hot socket detection circuit generates control signals that place the set of output transistors in a high impedance state.

    4.
    发明专利
    未知

    公开(公告)号：DE69933525T2

    公开(公告)日：2007-04-05

    申请号：DE69933525

    申请日：1999-11-15

    Applicant: ALTERA CORP

    Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

    IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

    Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

    TWO-TERMINAL MEMORY ARRAY WITH VARIABLE DEPTH AND WIDTH OF PROGRAMMABLE LOGIC ELEMENT
    7.
    发明专利
    TWO-TERMINAL MEMORY ARRAY WITH VARIABLE DEPTH AND WIDTH OF PROGRAMMABLE LOGIC ELEMENT 失效

    公开(公告)号：JPH11250667A

    公开(公告)日：1999-09-17

    申请号：JP29122198

    申请日：1998-10-13

    Applicant: ALTERA CORP

    Inventor： REDDY SRINIVAS T ,  LANE CHRISTOPHER F ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  VEENSTRA KERRY

    IPC: G11C11/41 ,  G11C7/10

    Abstract: PROBLEM TO BE SOLVED: To write a data word into an array and at the same time read it from the array by independently operating a write row decoder, a data selection logic, and a write row address decoder and then a read row decoder, a data selection logic, and a read row address decoder. SOLUTION: A write address is transmitted to a write column address decoder 100, a write row decoder, and a data selection logic 106. A read address is transmitted to a read column address decoder 113, a read row decoder, and a data selection logic 120. On the other hand, an input multiplexer 100 independently transmits a write enable signal and a read permission signal to write enable 114 and read enable 140. A control logic 116 independently sets a secondary write enable means (WE) 118 and a secondary read enable means (RE) 142 to a higher level.

    8.
    发明专利
    未知

    公开(公告)号：DE69933525D1

    公开(公告)日：2006-11-23

    申请号：DE69933525

    申请日：1999-11-15

    Applicant: ALTERA CORP

    Inventor： JEFFERSON DAVID E ,  LEE ANDY L ,  LANE CHRISTOPHER F ,  MCCLINTOCK CAMERON ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  SCHLEICHER JAMES ,  PEDERSON BRUCE B ,  REDDY SRINIVAS T

    IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

    Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

    9.
    发明专利
    未知

    公开(公告)号：DE69925982D1

    公开(公告)日：2005-08-04

    申请号：DE69925982

    申请日：1999-11-26

    Applicant: ALTERA CORP

    Inventor： MEJIA MANUEL

    IPC: G06F3/00 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003 ,  H03K19/0185

    Abstract: A circuit includes an output node, a set of output transistors operative to control the signal level on the output node, a first voltage supply, and a second voltage supply. A hot socket detection circuit identifies when the first voltage supply or the second voltage supply is below a predetermined value indicative of a hot socket condition. In response to a hot socket condition, the hot socket detection circuit generates control signals that place the set of output transistors in a high impedance state.

    Hierarchical interconnect for programmable logic devices
    10.
    发明专利
    Hierarchical interconnect for programmable logic devices 未知

    公开(公告)号：GB2318663A

    公开(公告)日：1998-04-29

    申请号：GB9718147

    申请日：1997-08-27

    Applicant: ALTERA CORP

    Inventor： REDDY SRINIVAS ,  MEJIA MANUEL

    IPC: H03K19/177

    Abstract: A hierarchical interconnect structure between logic elements LE, logic array blocks and global interconnects in a programmable logic device provides a first group 104 of local interconnect lines that couple to outputs of more than one logic element in a block, and a second group 106 of local interconnect lines that are divided into independent segments coupled to a subset of the logic elements in a block. By eliminating the one-to-one correspondence between the number of logic elements in a logic array block and the number of local interconnect wires, the present invention makes possible the inclusion of more logic elements in one block in an area efficient manner.

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