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    Programmable transceivers that are able to operate over wide frequency ranges
    2.
    发明专利
    Programmable transceivers that are able to operate over wide frequency ranges 有权
    可编程的收发器，可以在宽频范围内运行

    公开(公告)号：JP2007159110A

    公开(公告)日：2007-06-21

    申请号：JP2006303328

    申请日：2006-11-08

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY Y ,  PATEL RAKESH

    IPC: H03K19/173 ,  H01L21/822 ,  H01L27/04 ,  H03L7/08 ,  H04L7/033

    CPC classification number: H03K19/17744 ,  H03L7/0995

    Abstract: PROBLEM TO BE SOLVED: To provide an FPGA transceiver capable of operating over extremely wide frequency ranges. SOLUTION: A field-programmable gate array (FPGA) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first PLL may not be adequate to meet some possible needs. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够在极宽频率范围内工作的FPGA收发器。 解决方案：现场可编程门阵列（FPGA）可以包括数据接收器和/或发射器电路，其适于以宽范围的任何频率或数据速率接收和/或发送数据 可能的频率或数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在第一PLL的抖动性能不足以满足一些可能需要的情况下。 版权所有（C）2007，JPO＆INPIT

    Apparatus and methods for programmable slew rate control in transmitter circuits
    3.
    发明专利
    Apparatus and methods for programmable slew rate control in transmitter circuits 审中-公开
    发射机电路可编程速率控制的装置和方法

    公开(公告)号：JP2007028619A

    公开(公告)日：2007-02-01

    申请号：JP2006192210

    申请日：2006-07-12

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： ASADUZZAMAN KAZI ,  SHUMARAYEV SERGEY Y ,  TRAN THUNGOC M ,  WONG WILSON ,  PATEL RAKESH

    IPC: H03K19/0175 ,  H03K5/12 ,  H03K17/687

    CPC classification number: H03K17/164

    Abstract: PROBLEM TO BE SOLVED: To variably control a slew rate in a transmitter to be used for data transfer employing variable slew rate or various transmission protocols.
    SOLUTION: A transmitter driver circuit having a variable slew rate provided by the present invention comprises a pre-driver circuit for generating a driver input signal with a variable slew rate and a driver circuit for receiving a slew rate controlled signal from the pre-driver circuit. The pre-driver circuit comprises a plurality of pre-driver stages each selectively operable to drive a pre-driver output signal related to a signal received at an input and a control circuit which responds to at least one slew rate control signal, the control circuit operates to selectively enable the pre-driver stages and to change a pre-driver output signal slew rate, and the driver circuit generates a driver output signal with a slew rate related to a slew rate of the pre-driver output signal.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：可变地控制用于使用可变转换速率或各种传输协议的数据传输的发射机中的压摆率。 解决方案：由本发明提供的具有可变转换速率的发射器驱动电路包括用于产生具有可变转换速率的驱动器输入信号的预驱动器电路和用于从预先接收压摆率控制信号的驱动电路 驱动电路。 预驱动器电路包括多个预驱动器级，每个预驱动器级可选择性地操作以驱动与在输入处接收到的信号相关的预驱动器输出信号和响应于至少一个压摆率控制信号的控制电路，控制电路 操作以选择性地启用预驱动器级并改变预驱动器输出信号转换速率，并且驱动器电路产生具有与预驱动器输出信号的转换速率相关的转换速率的驱动器输出信号。 版权所有（C）2007，JPO＆INPIT

    Programmable logic device architecture for accommodating specialized circuity
    5.
    发明专利
    Programmable logic device architecture for accommodating specialized circuity 审中-公开
    适用于专用电路的可编程逻辑器件架构

    公开(公告)号：JP2007089150A

    公开(公告)日：2007-04-05

    申请号：JP2006237090

    申请日：2006-09-01

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY Y ,  RAKESH PATEL H ,  LEE CHONG H

    IPC: H03K19/173 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC classification number: H03K19/17704 ,  H03K19/17732 ,  H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic device (PLD) which supports specialized circuitry at different levels. SOLUTION: The programmable logic device (PLD) having one or more programmable logic (PL) regions (11) and one or more conventional input/output regions additionally has one or more peripheral areas (311-314) including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the PLD and one or both of the PL regions and the conventional I/O regions (and may be made on separate dies from the remainder of the PLD mounted on a common substrate) have contacts for metallization traces (35) or other interconnections to connect the peripheral specialized regions to the remainder of the PLD. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnection. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供支持不同级别的专用电路的可编程逻辑器件（PLD）。 解决方案：具有一个或多个可编程逻辑（PL）区域（11）和一个或多个常规输入/输出区域的可编程逻辑器件（PLD）还具有包括专用电路的一个或多个外围区域（311-314）。 不连接到PLD的其余部分和PL区域和常规I / O区域中的一个或两个的周边专用区域（并且可以在与安装在公共基板上的PLD的其余部分分开的管芯上制成） 具有用于金属化迹线（35）或其它互连的触点，以将外围专用区域连接到PLD的其余部分。 通过提供或不提供互连，同样的PLD可以通过或不具有专门的电路能力出售。 外围专业区域可能包括高速I / O（基本，高达约3 Gbps，增强，高达10-12 Gbps）以及其他类型的专用电路。 版权所有（C）2007，JPO＆INPIT

    Serializer circuitry for high-speed serial data transmitter on programmable logic device integrated circuit
    6.
    发明专利
    Serializer circuitry for high-speed serial data transmitter on programmable logic device integrated circuit 审中-公开
    用于可编程逻辑器件集成电路的高速串行数据发送器的串行电路

    公开(公告)号：JP2007043716A

    公开(公告)日：2007-02-15

    申请号：JP2006211485

    申请日：2006-08-02

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： NGUYEN TOAN THANH ,  TRAN THUNGOC ,  SHUMARAYEV SERGEY Y ,  ZALIZNYAK ARCH ,  WANG SHOUJUN ,  VENKATA RAMANAND ,  LEE CHONG

    IPC: H03K19/173

    CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

    Abstract: PROBLEM TO BE SOLVED: To provide serializer circuitry for executing serializing of parallel data at a data speed over a wide range under many different communication protocols. SOLUTION: The serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device ("PLD") or the like includes circuitry 10 for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects and at least some of the configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD). COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供串行器电路，用于在许多不同的通信协议下以宽范围的数据速度执行并行数据的串行化。 解决方案：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路10。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，并且可以动态地控制至少一些配置/重新配置（即在PLD的用户模式操作期间）。 版权所有（C）2007，JPO＆INPIT

    High-speed data receiving circuit network and method
    9.
    发明专利
    High-speed data receiving circuit network and method 有权
    高速数据接收电路和方法

    公开(公告)号：JP2007037114A

    公开(公告)日：2007-02-08

    申请号：JP2006187052

    申请日：2006-07-06

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY Y ,  WONG WILSON ,  PATEL RAKESH

    IPC: H04L25/03 ,  H04B3/06

    CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit network which compensates losses, such as decrease in signal amplitude and abrupt changes, in order to maintain accurate and high-speed data transmission.
    SOLUTION: An equalizing circuit network (10), receiving a digital data signal, includes both a feedforward equalizer (FFE)(30) and a determination feedback equalizer (DFE)(90). The FFE circuit network (30) is used for providing at least sufficient minimum signal to the DFE circuit network (90) and an adequate startup of the DFE circuit network (90). Accordingly, the heavier the load of an equalizing task is, the more the task can be shifted, from the FFE circuit network (30) to the DFE circuit network (90).
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供补偿诸如信号幅度和突然变化的损失的电路网络，以便保持精确和高速的数据传输。 解决方案：接收数字数据信号的均衡电路网络（10）包括前馈均衡器（FFE）（30）和确定反馈均衡器（DFE）（90）。 FFE电路网络（30）用于向DFE电路网络（90）提供至少足够的最小信号和DFE电路网络（90）的适当启动。 因此，平衡任务的负担越重，任务可以从FFE电路网络（30）到DFE电路网络（90）的移动越多。 版权所有（C）2007，JPO＆INPIT

    Multi-channel communications network for integrated circuitry, such as programmable logic device
    10.
    发明专利
    Multi-channel communications network for integrated circuitry, such as programmable logic device 审中-公开
    用于集成电路的多通道通信网络，如可编程逻辑器件

    公开(公告)号：JP2007028614A

    公开(公告)日：2007-02-01

    申请号：JP2006190911

    申请日：2006-07-11

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： TRAN THUNGOC ,  SHUMARAYEV SERGEY Y ,  HOANG TIM TRI ,  XUE NING ,  LEE CHONG ,  VENKATA RAMANAND

    IPC: H03K19/173 ,  H04J99/00

    CPC classification number: H03K19/17736 ,  H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To reduce a downstream network load due to synchronization generated between the outputs of a four channel system, when four or more channels operate simultaneously. SOLUTION: The integrated circuit such as a programmable logic device (PLD) or the like includes multiple channels (30-0 to 30-3) of data communications circuitry. Circuitry is (54, 60) provided between these channels which are grouped in various sizes so as to selectively share signals. Thus, the device can appropriately support a communication protocol requesting various numbers of channels. The shared signals can include a clock signal, or an FIFO writing/reading permission signal. The circuit is preferably arranged in modules (that is, a certain channel and adjacent channels thereof, and/or a channel in a certain group and channels in neighboring groups thereof are equivalent or substantially equivalent) for facilitating the circuit design, circuit checking or the like. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：当四个或更多个信道同时工作时，由于四通道系统的输出之间产生的同步而减少下游网络负载。 解决方案：诸如可编程逻辑器件（PLD）等的集成电路包括数据通信电路的多个通道（30-0至30-3）。 在这些通道之间提供电路（54,60），其被分组成各种尺寸以便选择性地共享信号。 因此，设备可以适当地支持请求各种信道数量的通信协议。 共享信号可以包括时钟信号或FIFO写入/读取许可信号。 电路优选地布置在模块中（即，某个信道及其相邻信道，和/或某个组中的信道，并且相邻组中的信道相当于或基本相等），以便于电路设计，电路检查或 喜欢。 版权所有（C）2007，JPO＆INPIT

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