公开(公告)号：JPH03188526A

公开(公告)日：1991-08-16

申请号：JP26035990

申请日：1990-09-28

Applicant: APPLE COMPUTER

Inventor： AREN JIEI BOOMU

IPC: G06F9/305 ,  G06F9/34

Abstract: PURPOSE: To enable contents of a prefix register to be connected to any number of following use commands and be used by extending the sign bit of a first value in the register and obtaining a second value from this value and using the second value as a parameter for program. CONSTITUTION: A prefix register PfxR stores values supplied by prefix commands; and if the prefix register is empty at the time of execution of a prefix command, the direct field of the prefix register is stored in lower bits of the prefix register, and the sign is extended. When another prefix command is continuously executed, contents of the prefix register are shifted left, and the direct field of the second prefix command is stored in lower bits of the prefix register which are made empty by left shift. When the prefix register is loaded, a prefix effective flag PV is set; and this flag is checked when a command having a prefixable direct field or displacement field is executed. Thus, contents of the prefix register PfxR are connected to the direct field or the displacement field of the command when the prefix effective flag PV is set.

公开(公告)号：JPH0340169A

公开(公告)日：1991-02-20

申请号：JP16148990

申请日：1990-06-21

Applicant: APPLE COMPUTER

Inventor： AREN JIEI BOOMU ,  MAIRON EICHI MAKUDOGARU

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/177

Abstract: PURPOSE: To realize inter-processor control/synchronization by providing an accessable global status register means where plural operation status codes are stored and indicating one of operation modes in a corresponding processor by plural operation status codes. CONSTITUTION: Four independent processors(PU) 12a to 12d access an instruction cache and a data cache through mutual connection networks 22 and 24 and individually have copies of prescribed special registers and share partial special registers (global registers) with one another. PUs are operated in a user mode or a system mode, and the mode of a PU at an arbitrary time is determined by setting of flags in PU status/control registers; and for example, when a start instruction, a restart instruction, and a transmission instruction are used, one PU can transmit an instruction address or a data value to another PU by one operation. Thus, inter-processor control/synchronization is realized.