公开(公告)号：JPH0340169A

公开(公告)日：1991-02-20

申请号：JP16148990

申请日：1990-06-21

Applicant: APPLE COMPUTER

Inventor： AREN JIEI BOOMU ,  MAIRON EICHI MAKUDOGARU

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/177

Abstract: PURPOSE: To realize inter-processor control/synchronization by providing an accessable global status register means where plural operation status codes are stored and indicating one of operation modes in a corresponding processor by plural operation status codes. CONSTITUTION: Four independent processors(PU) 12a to 12d access an instruction cache and a data cache through mutual connection networks 22 and 24 and individually have copies of prescribed special registers and share partial special registers (global registers) with one another. PUs are operated in a user mode or a system mode, and the mode of a PU at an arbitrary time is determined by setting of flags in PU status/control registers; and for example, when a start instruction, a restart instruction, and a transmission instruction are used, one PU can transmit an instruction address or a data value to another PU by one operation. Thus, inter-processor control/synchronization is realized.