公开(公告)号：BR112013003850A2

公开(公告)日：2016-07-05

申请号：BR112013003850

申请日：2011-08-11

Applicant: APPLE INC

Inventor： BEAUMONT-SMITH ANDREW J ,  LILLY BRIAN P ,  PATWARDHAN JAIDEV P ,  BANNON PETER J ,  GUNNA RAMESH ,  WEN SHIH-CHIEH R ,  YEH TSE-YU ,  LIEN WEI-HAN

IPC: G06F13/00

Abstract: buffer de escrita de combinação com medidas de esvaziamento dinamicamente ajustáveis. a presente invenção refere-se a um buffer de escrita de combinação que, em uma modalidade, é configurado para manter uma ou mais medidas de esvaziamento para determinar quando é para transmitir operações de escrita a partir de entradas de buffer. o buffer de escrita de combinação pode ser configurado para modificar dinamicamente as medidas de esvaziamento, em resposta a uma atividade no buffer de escrita, modificando as condições segundo as quais as operações de escrita são transmitidas a partir do buffer de escrita para o próximo nível mais baixo de memória. por exemplo, em uma implementação, as medidas de esvaziamento podem incluir entradas de buffer de escrita de categorização, tais como "colapsado". uma entrada de buffer de escrita colapsado e as operações de escrita colapsadas ali podem incluir pelo menos uma operação de escrita que tenha dados sobrescritos que foram escritos por uma operação de escrita prévia na entrada de buffer. em uma outra implementação, a combinação do buffer de escrita pode manter o limite de ocupação plena de buffer como uma medida de esvaziamento e pode ajustá-lo ao longo do tempo, com base na ocupação plena de buffer real.

公开(公告)号：AU2012227209B2

公开(公告)日：2014-01-23

申请号：AU2012227209

申请日：2012-09-19

Applicant: APPLE INC

Inventor： MURRAY DANIEL C ,  BEAUMONT-SMITH ANDREW J ,  MYLIUS JOHN H ,  BANNON PETER J ,  TAKAYANAGI TOSHI ,  CHO JUNG WOOK

IPC: G06F1/32

Abstract: A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable. Power Management 200 Power Manager 2 Power Processor Core Manager 100 State Machine Power State Table Power __ _ _ _ __ _ _ _ Powerr State Entry Power Code 240a Throttle Unit Entry 150 240b - Throttle Code, Other Throttle Entry Parameters Code, 240g Other Paramete Config u ration Power Operational Operational Throttle Register State Code Frequency Voltage Code 270 242 244 246 248 Throttle Code, Other Software Layer Parameters

公开(公告)号：AU2011292293B2

公开(公告)日：2014-02-06

申请号：AU2011292293

申请日：2011-08-11

Applicant: APPLE INC

Inventor： BANNON PETER J ,  BEAUMONT-SMITH ANDREW J ,  GUNNA RAMESH ,  LIEN WEI-HAN ,  PATWARDHAN JAIDEV P ,  LILLY BRIAN P ,  WEN SHIH-CHIEH R ,  YEH TSE-YU

IPC: G06F13/00

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as "collapsed." A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

公开(公告)号：BR102012024721A2

公开(公告)日：2013-11-26

申请号：BR102012024721

申请日：2012-09-27

Applicant: APPLE INC

Inventor： MURRAY DANIEL C ,  BEAUMONT-SMITH ANDREW J ,  MYLIUS JOHN H ,  BANNON PETER J ,  YANAGI TOSHI TAKA ,  CHO JUNG WOOK

IPC: G01R31/26 ,  G06F11/30 ,  H01L23/34

Abstract: A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.

公开(公告)号：AU2012227209A1

公开(公告)日：2013-05-16

申请号：AU2012227209

申请日：2012-09-19

Applicant: APPLE INC

Inventor： MURRAY DANIEL C ,  BEAUMONT-SMITH ANDREW J ,  MYLIUS JOHN H ,  BANNON PETER J ,  TAKAYANAGI TOSHI ,  CHO JUNG WOOK

IPC: G06F1/32

Abstract: A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable. Power Management 200 Power Manager 2 Power Processor Core Manager 100 State Machine Power State Table Power __ _ _ _ __ _ _ _ Powerr State Entry Power Code 240a Throttle Unit Entry 150 240b - Throttle Code, Other Throttle Entry Parameters Code, 240g Other Paramete Config u ration Power Operational Operational Throttle Register State Code Frequency Voltage Code 270 242 244 246 248 Throttle Code, Other Software Layer Parameters

公开(公告)号：MX2013001941A

公开(公告)日：2013-03-18

申请号：MX2013001941

申请日：2011-08-11

Applicant: APPLE INC

Inventor： LILLY BRIAN P ,  BANNON PETER J ,  BEAUMONT-SMITH ANDREW J ,  GUNNA RAMESH ,  LIEN WEI-HAN ,  PATWARDHAN JAIDEV P ,  WEN SHIH-CHIEH R ,  YEH TSE-YU

IPC: G06F13/00

Abstract: En una modalidad, una combinación de memoria temporal de escritura se configura para mantener una o más métricas de vaciado para determinar cuándo se transmiten las operaciones de escritura desde las entradas de la memoria temporal. La combinación de la memoria temporal de escritura puede configurarse para modificar dinámicamente las métricas de vaciado en respuesta a la actividad en la memoria temporal de escritura, modificando las condiciones bajo las cuales las operaciones de escritura se transmiten desde la memoria temporal de escritura al siguiente nivel menor de memoria. Por ejemplo, en una implementación, las métricas de vaciado pueden incluir categorizar las entradas de la memoria temporal de escritura como "colapsadas". Una entrada de memoria temporal de escritura colapsada y las operaciones de escritura colapsadas en la misma, pueden incluir al menos una operación de escritura que tiene datos sobre escritos que se escribieron por una operación de escritura previa en la entrada de la memoria temporal. En otra implementación, la combinación de la memoria temporal de escritura puede mantener el inicio de la plenitud del vaciado como una métrica de vaciado y puede ajustarlo en el tiempo con base en la plenitud de vaciado real.

公开(公告)号：AU2011292293A1

公开(公告)日：2013-02-21

申请号：AU2011292293

申请日：2011-08-11

Applicant: APPLE INC

Inventor： BANNON PETER J ,  BEAUMONT-SMITH ANDREW J ,  GUNNA RAMESH ,  LIEN WEI-HAN ,  PATWARDHAN JAIDEV P ,  LILLY BRIAN P ,  WEN SHIH-CHIEH R ,  YEH TSE-YU

IPC: G06F13/00

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as "collapsed." A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.