DYNAMIC LEAKAGE CONTROL FOR MEMORY ARRAYS

    公开(公告)号:HK1164531A1

    公开(公告)日:2012-09-21

    申请号:HK12104747

    申请日:2012-05-15

    Applicant: APPLE INC

    Abstract: A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.

    SYSTEM CACHE WITH STICKY REMOVAL ENGINE
    3.
    发明申请
    SYSTEM CACHE WITH STICKY REMOVAL ENGINE 审中-公开
    带有拆卸式发动机的系统缓存

    公开(公告)号:WO2014052589A3

    公开(公告)日:2014-08-28

    申请号:PCT/US2013061919

    申请日:2013-09-26

    Applicant: APPLE INC

    CPC classification number: G06F12/126 G06F1/3225 G06F12/0842

    Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

    Abstract translation: 用于释放用于一个或多个组ID的高速缓存行的粘性状态的方法和装置。 粘性移除引擎遍历系统缓存的标签存储器,寻找与从系统高速缓存清除其高速缓存行的第一组ID的匹配。 引擎清除属于第一组ID的每个高速缓存行的粘性状态。 如果引擎接收到第二组ID的释放请求,则引擎记录当前索引以通过标记存储器记录其进度。 然后,引擎继续通过标签存储器查找与第一或第二组ID的匹配。 发动机卷绕到标签存储器的开头,并继续其行进直到到达第二组ID的记录索引。

    INTEGRATED CIRCUIT WITH MULTIPORTED MEMORY SUPERCELL AND DATA PATH SWITCHING CIRCUITRY
    4.
    发明公开
    INTEGRATED CIRCUIT WITH MULTIPORTED MEMORY SUPERCELL AND DATA PATH SWITCHING CIRCUITRY 审中-公开
    随着越来越多端口存储器,超级单元和数据路径替代电路集成电路

    公开(公告)号:EP2396886A4

    公开(公告)日:2015-09-02

    申请号:EP10741767

    申请日:2010-02-12

    Applicant: APPLE INC

    Abstract: An integrated circuit. The integrated circuit includes a plurality of memory requesters and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the memory supercell is organized into a plurality of bank groups. Each of the plurality of bank groups includes a subset of the plurality of memory banks and a corresponding dedicated access port. The integrated circuit further includes a switch coupled between the plurality of memory requesters and the memory supercell. The switch is configured, responsive to a memory request by a given one of the plurality of memory requesters, to connect a data path between the given memory requester and the dedicated access port of a particular one of the bank groups addressed by the memory request.

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