公开(公告)号：WO2018226302A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024814

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/32

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：WO2018226301A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024813

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/32

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：WO2018226300A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024811

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.