公开(公告)号：WO2018226302A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024814

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/32

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：WO2014092840A1

公开(公告)日：2014-06-19

申请号：PCT/US2013/062024

申请日：2013-09-26

Applicant: APPLE INC.

Inventor： DORSEY, John G. ,  ISMAIL, James S. ,  COX, Keith ,  KAPOOR, Gaurav

IPC: G06F1/26 ,  G06F1/08

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract translation: 本发明提供了一种用于针对包括在计算设备中的处理器的电压和/或频率进行目标缩放的技术。 一个实施例涉及基于每秒输入帧缓冲器的帧数来缩放处理器的电压/频率，以便减少或消除在计算设备的显示器上显示的动画中的笨拙。 本发明的另一实施例涉及基于GPU的利用率来缩放处理器的电压/频率，以便减少或消除由CPU向GPU缓慢发出指令所引起的任何瓶颈。 本发明的另一个实施例涉及根据由CPU执行的特定类型的指令来调整CPU的电压/频率。 另外的实施例包括在CPU执行具有传统台式/膝上型计算机应用的特征的工作负载时缩放CPU的电压和/或频率。

公开(公告)号：WO2018226301A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024813

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/32

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：WO2018226300A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024811

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.