公开(公告)号：WO2018226302A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024814

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/32

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：WO2013074201A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/056902

申请日：2012-09-24

Applicant: APPLE INC. ,  VAISHAMPAYAN, Umesh S. ,  CHIMENE, Daniel A. ,  HELLER, Daniel S.

Inventor： VAISHAMPAYAN, Umesh S. ,  CHIMENE, Daniel A. ,  HELLER, Daniel S.

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/3466 ,  G06F12/0253

Abstract: Techniques for tracking memory usages of a data processing system are described herein. According to one embodiment, a memory manager is to perform a first lookup operation in a memory allocation table to identify an allocation entry based on a handle representing a memory address of a memory block allocated to a client and to retrieve a trace entry pointer from the allocation entry. The memory manager is then to perform a second lookup operation in a memory trace table to identify a trace entry based on the trace entry pointer and to increment a memory allocation count of the trace entry. The memory allocation count is utilized to indicate a likelihood of the client causing a memory leak.

Abstract translation: 本文描述了用于跟踪数据处理系统的存储器使用的技术。 根据一个实施例，存储器管理器将在存储器分配表中执行第一查找操作以基于表示分配给客户端的存储器块的存储器地址的句柄来识别分配条目，并且从所述存储器分配表中检索跟踪条目指针 分配条目。 然后，存储器管理器在存储器跟踪表中执行第二查找操作，以基于跟踪条目指针识别跟踪条目，并增加跟踪条目的存储器分配计数。 存储器分配计数用于指示客户端造成内存泄漏的可能性。

公开(公告)号：WO2018226301A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024813

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/48 ,  G06F9/50 ,  G06F1/32

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：WO2018226300A1

公开(公告)日：2018-12-13

申请号：PCT/US2018/024811

申请日：2018-03-28

Applicant: APPLE INC.

Inventor： ANDRUS, Jeremy C. ,  DORSEY, John G. ,  MAGEE, James M. ,  CHIMENE, Daniel A. ,  DE LA CROPTE DE CHANTERAC, Cyril ,  HINCH, Bryan R. ,  VENKATARAMAN, Aditya ,  DOROFEEV, Andrei ,  GAMBLE, Nigel R. ,  BLAINE, Russell A. ,  PISTOL, Constantin

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.