公开(公告)号：WO2017014949A1

公开(公告)日：2017-01-26

申请号：PCT/US2016/041139

申请日：2016-07-06

Applicant: APPLE INC.

Inventor： LEE, Meng Chi ,  CHAUHAN, Shakti S. ,  CARSON, Flynn P. ,  HSU, Jun Chung ,  LIN, Tha-An

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/58

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Abstract translation: 公开了一种封装系统（SiP），其使用EMI屏蔽来抑制SiP内的元件上的EMI或其他电干扰。 可以在SiP上形成金属屏蔽。 金属屏蔽可以电耦合到印刷电路板（PCB）中的接地层，以在SiP周围形成EMI屏蔽。 SiP的衬底可以包括在衬底的端部中沿垂直壁的至少一些金属化。 金属化可以提供用于将金属屏蔽件耦合到耦合到PCB中的接地层的接地环的大的接触面积。 沿着衬底的端部的垂直壁的金属化可以在共形衬底之前形成为通孔，以形成SiP。

公开(公告)号：WO2023033913A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/035676

申请日：2022-06-30

Applicant: APPLE INC.

Inventor： DALMIA, Sidharth S. ,  YUN, Wansuk ,  CARSON, Flynn P.

IPC: H01Q21/06 ,  H01Q1/24 ,  H01Q5/20 ,  H01Q1/38 ,  H01L23/26 ,  H01L23/498

Abstract: A radio frequency package includes a first portion of an antenna array module, a second portion of the antenna array module, and a flexible cable. The first portion of the antenna array module provides a first wireless communication functionality and the second portion of the antenna array module provides a second wireless communication functionality. The flexible cable includes first surface directly coupled to the first portion of the antenna array module. The flexible cable also includes a second surface directly coupled to the second portion of the antenna array module. The flexible cable communicates signals between the first portion of the distributed antenna array module and the second portion of the antenna array module.

公开(公告)号：WO2022108776A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/058397

申请日：2021-11-08

Applicant: APPLE INC.

Inventor： SHANMUGAM, Karthik ,  CARSON, Flynn P. ,  ZHAI, Jun ,  CAMENFORTE, Raymundo M. ,  LI, Menglu

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/00

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：WO2017078849A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/051479

申请日：2016-09-13

Applicant: APPLE INC.

Inventor： HSU, Jun Chung ,  CARSON, Flynn P. ,  LAI, Kwan-Yu

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/46

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a "known good" substrate on a support substrate.

Abstract translation: 描述了形成超薄无芯基板的方法。 在一个实施例中，该方法利用包括高和低粘附表面区域的剥离层到载体基底，并切割低粘附表面区域以从载体基底去除堆积结构。 电短层可以形成为脱粘层的一部分或在脱粘层上，以便于在脱粘之前对增层结构进行电测试，并有助于形成“已知良好”的结构。 衬底在支撑衬底上。

公开(公告)号：WO2016081182A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/058474

申请日：2015-10-30

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  CARSON, Flynn P.

IPC: H01L25/03 ,  H01L21/98 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/552 ,  H01L24/19 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2224/81

Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the second routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.

Abstract translation: 描述了扇出晶片级封装（FOWLP）和形成方法。 在一个实施例中，包装包括第一布线层，第一布线层的顶侧上的第一管芯，以及将第一管芯封装在第一布线层上的第一模制化合物。 第一多个导电柱从第一路由层的底侧延伸。 第二管芯位于第二布线层的顶侧，并且第一多个导电柱位于第二布线层的顶侧。 第二模塑料在第二路由层上封装第一模塑料，第一路由层，第一多个导电柱和第二模。 在一个实施例中，多个导电凸块（例如焊球）从第二布线层的底侧延伸。