公开(公告)号：WO2023049597A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/075471

申请日：2022-08-25

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  YEH, Jung-Cheng ,  HU, Kunzhong ,  CAMENFORTE, Raymundo ,  HOFFMANN, Thomas

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L23/66

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：WO2020112505A3

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60 ,  H01L23/29

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure (310) to connect a die set (110, 110) embedded in an inorganic gap fill material (130).

公开(公告)号：WO2020112505A2

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：WO2022066364A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/048174

申请日：2021-08-30

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  CAO, Zhitao ,  HU, Kunzhong

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/00

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

公开(公告)号：WO2023019070A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/074392

申请日：2022-08-01

Applicant: APPLE INC.

Inventor： RAMACHANDRAN, Vidhya ,  DABRAL, Sanjay ,  JANGAM, SivaChandra ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：WO2022191974A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/016785

申请日：2022-02-17

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  NI, Chi Nung ,  HUANG, Long ,  JANGAM, SivaChandra

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/528 ,  H01L23/66

Abstract: Chip sealing structures which can accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure. In other embodiments, sealed box structures are described in which the die-to-die routing jumps over the seal structures, or is formed on a back side of the semiconductor substrate and connected to through silicon vias. In yet other embodiments, electromagnetic field communication structures are described to accommodate wireless die-to-die communication across sealing structures without physical wiring.

公开(公告)号：WO2021158419A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/015441

申请日：2021-01-28

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  CAO, Zhitao ,  HU, Kunzhong ,  ZHAI, Jun

IPC: H01L23/50 ,  H01L23/538

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：WO2019199472A1

公开(公告)日：2019-10-17

申请号：PCT/US2019/024647

申请日：2019-03-28

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  KILIC, Bahattin ,  ZHAO, Jie-Hua ,  HU, Kunzhong ,  RYU, Suk-Kyu

IPC: H01L23/00 ,  H01L25/065 ,  G06F13/40 ,  G06F15/78

Abstract: Multi-chip systems (100) and structures for modular scaling are described. In some embodiments an interfacing bar (150) is utilized to couple adjacent chips (102, 104). For example, a communication bar (150) may utilized to coupled logic chips (104), and memory bar (150) may be utilized to couple multiple memory chips (102) to a logic chip (104).