公开(公告)号：WO2022056206A1

公开(公告)日：2022-03-17

申请号：PCT/US2021/049777

申请日：2021-09-10

Applicant: APPLE INC.

Inventor： VASH, James ,  GARG, Gaurav ,  LILLY, Brian P. ,  GUNNA, Ramesh B. ,  HUTSELL, Steven R. ,  LEVY-RUBIN, Lital ,  HAMMARLUND, Per H.

IPC: G06F12/0817

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：EP4398115A2

公开(公告)日：2024-07-10

申请号：EP24167536.2

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, III Gerard R. ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesh B.

IPC: G06F13/10

CPC classification number: Y02D10/00 ,  G06F13/161 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/1668 ,  G06F15/7807 ,  G06F2212/104820130101 ,  G06F2212/102420130101 ,  G06F12/0824 ,  G06F12/0833 ,  G06F12/0813 ,  G06F2212/45520130101

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.

公开(公告)号：EP4398115A3

公开(公告)日：2025-01-15

申请号：EP24167536.2

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, III Gerard R. ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesh B.

IPC: G06F12/08

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.

公开(公告)号：EP4398114A3

公开(公告)日：2025-01-01

申请号：EP24165580.2

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, Gerard R. III ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesch B.

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.

公开(公告)号：EP4473413A1

公开(公告)日：2024-12-11

申请号：EP23750057.4

申请日：2023-01-12

Applicant: Apple Inc.

Inventor： NEMATI, Farid ,  HUTSELL, Steven R. ,  MATHEWS, Gregory S. ,  CHEN, Yi Chun ,  WONG, Kevin C. ,  BANSAL, Kalpana ,  KUMAR, Derek R. ,  SEMERIA, Bernard J. ,  VASH, James ,  NANGIA, Era K.

IPC: G06F11/10 ,  G06F13/16 ,  G06F9/30

公开(公告)号：EP4398114A2

公开(公告)日：2024-07-10

申请号：EP24165580.2

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, Gerard R. III ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesch B.

IPC: G06F13/10

CPC classification number: Y02D10/00 ,  G06F13/161 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/1668 ,  G06F15/7807 ,  G06F2212/104820130101 ,  G06F2212/102420130101 ,  G06F12/0824 ,  G06F12/0833 ,  G06F12/0813 ,  G06F2212/45520130101

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.