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    I/O AGENT
    1.
    发明申请
    I/O AGENT 审中-公开

    公开(公告)号：WO2022216597A1

    公开(公告)日：2022-10-13

    申请号：PCT/US2022/023296

    申请日：2022-04-04

    Applicant: APPLE INC.

    Inventor： GARG, Gaurav ,  LAHAV, Sagi ,  LEVY-RUBIN, Lital ,  WILLIAMS, III, Gerard ,  NASSAR, Samer ,  HAMMARLUND, Per H. ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  GONION, Jeff ,  VASH, James

    IPC: G06F12/0831

    Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

    DSB OPERATION WITH EXCLUDED REGION
    2.
    发明申请
    DSB OPERATION WITH EXCLUDED REGION 审中-公开

    公开(公告)号：WO2022056187A1

    公开(公告)日：2022-03-17

    申请号：PCT/US2021/049750

    申请日：2021-09-10

    Applicant: APPLE INC.

    Inventor： GONION, Jeff ,  KELM, John H. ,  VASH, James ,  KANAPATHIPILLAI, Pradeep ,  AGARWAL, Mridul ,  LEVINSKY, Gideon N. ,  RUSSO, Richard F. ,  TSAY, Christopher M.

    IPC: G06F9/52 ,  G06F12/0831 ,  G06F12/1027 ,  G06F15/78

    Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

    SCALABLE CACHE COHERENCY PROTOCOL
    4.
    发明申请
    SCALABLE CACHE COHERENCY PROTOCOL 审中-公开

    公开(公告)号：WO2022056206A1

    公开(公告)日：2022-03-17

    申请号：PCT/US2021/049777

    申请日：2021-09-10

    Applicant: APPLE INC.

    Inventor： VASH, James ,  GARG, Gaurav ,  LILLY, Brian P. ,  GUNNA, Ramesh B. ,  HUTSELL, Steven R. ,  LEVY-RUBIN, Lital ,  HAMMARLUND, Per H.

    IPC: G06F12/0817

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

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