公开(公告)号：WO2018026709A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/044668

申请日：2017-07-31

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HOLLAND, Peter F. ,  MACHNICKI, Erik P. ,  JETER, Robert E. ,  NOTANI, Rakesh L. ,  PARIK, Neeraj ,  SCHAUB, Marc A.

IPC: G06F13/16

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract translation: 在一些实施例中，系统包括存储器系统，实时计算设备和控制器。 实时计算设备将数据存储在具有对应的存储阈值的本地缓冲区内，其中数据满足存储阈值，并且其中存储阈值基于存储器系统的等待时间和预期的数据利用率 本地缓冲区。 控制器检测到存储器系统应当执行操作，其中存储器系统在操作期间对于实时计算设备不可用。 响应于检测到操作的时间量超过对应于存储阈值的时间量，控制器覆盖存储阈值。 控制器可以通过修改存储阈值并且通过超越实时计算设备对存储器系统的访问请求的默认优先级来覆盖存储阈值。

公开(公告)号：WO2022010673A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/039190

申请日：2021-06-25

Applicant: APPLE INC.

Inventor： SCHAUB, Marc A. ,  MOSS, Roy G.

IPC: G06F13/28

Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.