公开(公告)号：WO2015183404A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/023824

申请日：2015-04-01

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane, J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik, P. ,  HERBECK, Gilbert, H. ,  MILLET, Timothy, J. ,  DE CESARE, Joshua, P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：WO2017099861A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/051967

申请日：2016-09-15

Applicant: APPLE INC.

Inventor： YU, Shu-Yi ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  KATTEL, Kiran B. ,  GULATI, Manu

IPC: G06F1/12 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

Abstract translation: 在一个实施例中，诸如SOC（或者甚至是分立芯片系统）的集成电路在各个位置包括一个或多个本地时基。 时基可以基于在使用期间可能经历变化的高频本地时钟而增加。 周期性地，基于变化较小的较低频率的时钟，可以使用硬件电路将本地时基同步到正确的时间。 特别地，如果在同步之前本地时基达到正确值，则可以将用于下一同步的正确时基值传送给每个本地时基，并且可以将用于本地时基的控制电路配置为使本地时基饱和为正确的值 发生。 类似地，如果发生同步并且本地时基尚未达到正确值，则可以将控制电路配置为加载正确的时基值。

公开(公告)号：WO2015183377A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/020330

申请日：2015-03-13

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik, P. ,  HERBECK, Gilbert, H. ,  MILLET, Timothy, J. ,  DE CESARE, Joshua, P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：WO2018039362A1

公开(公告)日：2018-03-01

申请号：PCT/US2017/048237

申请日：2017-08-23

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  SHULER, Christopher D. ,  DODGE, Benjamin K. ,  VIJAYARAJ, Thejasvi M. ,  KAUSHIKKAR, Harshavardhan ,  YANG, Yang ,  HU, Rong Z. ,  SRIDHARAN, Srinivasa R. ,  KLINGAUF, Wolfgang H. ,  PARIK, Neeraj

IPC: G06F13/16 ,  G06F9/54 ,  H04L12/865

CPC classification number: H04L47/6295 ,  G06F9/546 ,  G06F13/1642 ,  H04L47/6275 ,  H04L49/109

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

Abstract translation: 在一些实施例中，系统包括存储器系统，多个计算设备和多个队列。 多个计算设备根据存储在存储设备处的数据执行动作，其中多个计算设备和存储设备之间的通信量具有至少第一优先级和第二优先级。 第一优先级高于第二优先级。 多个队列在存储器装置和多个计算装置之间传递数据。 特定队列将特定队列的第一部分分配给具有第一优先级的业务，并将特定队列的第二部分分配给具有第一优先级的业务和具有第二优先级的业务。

公开(公告)号：WO2017023420A1

公开(公告)日：2017-02-09

申请号：PCT/US2016/036688

申请日：2016-06-09

Applicant: APPLE INC.

Inventor： MILLET, Timothy J. ,  GULATI, Manu ,  SPENCE, Arthur L. ,  SAUND, Gurjeet S. ,  ESSER, Robert P.

IPC: G06F9/48

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

Abstract translation: 系统的实施例可以包括多个媒体单元，处理器和电路。 每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。 处理器可以被配置为在队列中存储多个媒体处理命令。 电路可以被配置为从队列检索第一媒体处理命令，并将第一媒体处理命令发送到第一媒体单元。 电路还可以被配置为响应于从第一媒体单元接收到中断而从队列中检索第二媒体处理并将第二媒体处理命令发送到第二媒体单元。 响应于接收到来自第一媒体单元的中断，电路可以将数据从第一媒体单元复制到第二媒体单元。

公开(公告)号：WO2016053490A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/045585

申请日：2015-08-17

Applicant: APPLE INC.

Inventor： DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  MACHNICKI, Erik P. ,  COX, Keith ,  MILLET, Timothy J.

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract translation: 公开了允许调整计算系统的性能设置的方法的实施例。 一个或多个功能单元可以包括多个监视器电路，每个监视器电路可以被配置为监视对应功能单元的给定操作参数。 在检测到与所监视的操作参数有关的事件时，监视器电路可产生中断。 响应于中断，处理器可以调整计算系统的一个或多个性能设置。

公开(公告)号：WO2014182393A1

公开(公告)日：2014-11-13

申请号：PCT/US2014/032811

申请日：2014-04-03

Applicant: APPLE INC.

Inventor： SUKALPA, Biswas ,  SHIU, Shinye ,  DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  DESAI, Pulkit ,  HU, Rong Zhang

IPC: G06F3/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/00

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

公开(公告)号：WO2018026709A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/044668

申请日：2017-07-31

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HOLLAND, Peter F. ,  MACHNICKI, Erik P. ,  JETER, Robert E. ,  NOTANI, Rakesh L. ,  PARIK, Neeraj ,  SCHAUB, Marc A.

IPC: G06F13/16

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract translation: 在一些实施例中，系统包括存储器系统，实时计算设备和控制器。 实时计算设备将数据存储在具有对应的存储阈值的本地缓冲区内，其中数据满足存储阈值，并且其中存储阈值基于存储器系统的等待时间和预期的数据利用率 本地缓冲区。 控制器检测到存储器系统应当执行操作，其中存储器系统在操作期间对于实时计算设备不可用。 响应于检测到操作的时间量超过对应于存储阈值的时间量，控制器覆盖存储阈值。 控制器可以通过修改存储阈值并且通过超越实时计算设备对存储器系统的访问请求的默认优先级来覆盖存储阈值。

公开(公告)号：WO2017058414A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/048697

申请日：2016-08-25

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  SOKOL Jr., Joseph ,  WILCOX, Jeffrey R. ,  SEMERIA, Bernard J. ,  SMITH, Michael J.

IPC: G06F12/02 ,  G06F21/72 ,  G11C7/24

CPC classification number: G06F12/0246 ,  G06F21/78 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

Abstract translation: 在一个实施例中，系统包括可用作主存储器系统和后备存储器（或持久存储器）两者的非易失性存储器。 在一些实施例中，非易失性存储器被分成主存储器部分和持久部分。 在一个实施例中，主存储器操作中的数据可以使用一个或多个第一密钥加密，并且持久部分中的数据可以使用一个或多个第二密钥进行加密。 主存储器的易失性行为可以通过在功率下降事件中丢弃一个或多个第一密钥或指示主存储器数据丢失的其他事件来实现，同时可以保留一个或多个第二密钥。 在一个实施例中，非易失性存储器的物理地址空间可以是来自在系统内使用的第二物理地址空间的映射。

公开(公告)号：WO2016130212A1

公开(公告)日：2016-08-18

申请号：PCT/US2015/066310

申请日：2015-12-17

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HERBECK, Gilbert H. ,  KOSUT, Alexei E. ,  JONES, Girault W. ,  MILLET, Timothy J.

IPC: G10L25/78 ,  G06F3/16 ,  G10L15/28

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。 在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。 响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。 在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。 电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。