公开(公告)号：WO1993006559A1

公开(公告)日：1993-04-01

申请号：PCT/US1992008115

申请日：1992-09-23

Applicant: APTIX CORPORATION

Inventor： APTIX CORPORATION ,  MOHSEN, Amr, M.

IPC: G06F15/60

CPC classification number: H03K17/002 ,  H01L23/525 ,  H01L2924/0002 ,  H03K17/693 ,  H01L2924/00

Abstract: A universal interconnect matrix area array (605) comprised of a first set of conductive leads (608-1 through 608-J) formed in a first direction, a second set of conductive leads (609-1 through 609-K) formed in a second direction, the second direction being not parallel to the first direction, and structure for electrically interconnecting selected ones of the conductive leads in the first set of conductive leads (608-1 through 608-J) to one or more of the conductive leads in the second set of conductive leads (609-1 through 609-K). Input/output pads (607-1,1 through 607-M,N) are formed and connected to selected ones of the first set of conductive leads (608-1 through 608-J) and second set of conductive leads (609-1 through 609-K). Selected ones of the conductive leads are segmented thereby to allow any input/output pad to be connected to one or more of the other input/output pads (607-1,1 through 607-M,N) without removing from use any input/output pads (607-1,1 through 607-M,N), not intended to be so connected.

Abstract translation: 由在第一方向上形成的第一组导电引线（608-1至608-J），第二组导电引线（609-1至609-K）形成的通用互连矩阵区阵列（605） 第二方向，第二方向不平行于第一方向，以及用于将第一组导电引线（608-1至608-J）中的导电引线中的一些导电引线与一个或多个导电引线电连接的结构 第二组导电引线（609-1至609-K）。 形成输入/输出焊盘（607-1,1至607-M，N）并将其连接到第一组导电引线（608-1至608-J）和第二组导电引线（609-1 通过609-K）。 所选择的导电引线被分段，从而允许任何输入/输出焊盘连接到一个或多个其它输入/输出焊盘（607-1,1到607-M，N），而不用使用任何输入/ 输出焊盘（607-1,1至607-M，N），不打算如此连接。

公开(公告)号：WO1994015399A1

公开(公告)日：1994-07-07

申请号：PCT/US1993012119

申请日：1993-12-16

Applicant: APTIX CORPORATION

Inventor： APTIX CORPORATION ,  VERHEYEN, Henry, T. ,  KRING, Charles J., Jr. ,  OSANN, Robert, Jr.

IPC: H03K17/693

CPC classification number: H03K19/17704 ,  H05K1/0286 ,  H05K1/18

Abstract: A programmable interconnect system includes a two-level hierarchical structure of programmable interconnect chips (120.1-120.6 and 130.1-130.2) on a circuit board (110). The first-level, or "local", interconnect chips are connected to user components (150.1-150.5). A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

Abstract translation: 可编程互连系统包括在电路板（110）上的可编程互连芯片（120.1-120.6和130.1-130.2）的两级分层结构。 第一级或“本地”互连芯片连接到用户组件（150.1-150.5）。 多个二级或“全局”互连芯片互连局部互连芯片，使得每个本地芯片连接到每个全局芯片。 这种系统允许通过最多三个互连芯片的导电路径将任何用户组件的任何引脚连接到任何用户组件的任何其他引脚。 即使在具有大量互连芯片的实施例中，也提供了大量这样的路径。