公开(公告)号：WO1994015399A1

公开(公告)日：1994-07-07

申请号：PCT/US1993012119

申请日：1993-12-16

Applicant: APTIX CORPORATION

Inventor： APTIX CORPORATION ,  VERHEYEN, Henry, T. ,  KRING, Charles J., Jr. ,  OSANN, Robert, Jr.

IPC: H03K17/693

CPC classification number: H03K19/17704 ,  H05K1/0286 ,  H05K1/18

Abstract: A programmable interconnect system includes a two-level hierarchical structure of programmable interconnect chips (120.1-120.6 and 130.1-130.2) on a circuit board (110). The first-level, or "local", interconnect chips are connected to user components (150.1-150.5). A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

Abstract translation: 可编程互连系统包括在电路板（110）上的可编程互连芯片（120.1-120.6和130.1-130.2）的两级分层结构。 第一级或“本地”互连芯片连接到用户组件（150.1-150.5）。 多个二级或“全局”互连芯片互连局部互连芯片，使得每个本地芯片连接到每个全局芯片。 这种系统允许通过最多三个互连芯片的导电路径将任何用户组件的任何引脚连接到任何用户组件的任何其他引脚。 即使在具有大量互连芯片的实施例中，也提供了大量这样的路径。