METHODS OF METROLOGY
    3.
    发明申请

    公开(公告)号:US20250147436A1

    公开(公告)日:2025-05-08

    申请号:US18832408

    申请日:2023-01-23

    Abstract: A method for determining a parameter of interest relating to at least one structure formed on a substrate in a manufacturing process. The method includes: obtaining layout data relating to a layout of a pattern to be applied to the at least one structure, the pattern including the at least one structure; and obtaining a trained model, having been trained on metrology data and the layout data to infer a value and/or probability metric relating to a parameter of interest from at least the layout data, the metrology data relating to a plurality of measurements of the parameter of interest at a respective plurality of measurement locations on the substrate. A value and/or probability metric is determined relating to the parameter of interest at one or more locations on the substrate different from the measurement locations from at least layout data using the trained model.

    METHOD OF DETERMINING MARK STRUCTURE FOR OVERLAY FINGERPRINTS

    公开(公告)号:US20230408931A1

    公开(公告)日:2023-12-21

    申请号:US18035286

    申请日:2021-11-01

    Abstract: An apparatus and a method for generating a metrology mark structure that can be formed on a substrate for measuring overlay characteristics induced by one or more processes performed on the substrate by determining features for the metrology mark structure based on a pattern distribution. The method involves obtaining a function to characterize an overlay fingerprint induced by a process performed on a substrate. Based on the function, a pattern distribution is derived, the pattern distribution being indicative of a number of features (e.g., indicative of density) within a portion of the substrate. Based on the pattern distribution, a physical characteristic (e.g., shape, size, etc.) of the features of the metrology mark structure is determined.

    METHOD FOR APPLYING A DEPOSITION MODEL IN A SEMICONDUCTOR MANUFACTURING PROCESS

    公开(公告)号:US20220350254A1

    公开(公告)日:2022-11-03

    申请号:US17621494

    申请日:2020-06-04

    Abstract: A method for applying a deposition model in a semiconductor manufacturing process. The method includes predicting a deposition profile of a substrate using the deposition model; and using the predicted deposition profile to enhance a metrology target design. The deposition model can be calibrated using experimental cross-section profile information from a layer of a physical substrate. In some embodiments, the deposition model is a machine-learning model, and calibrating the deposition model includes training the machine-learning model. The metrology target design may include an alignment metrology target design or an overlay metrology target design, for example.

Patent Agency Ranking