公开(公告)号：AU9089501A

公开(公告)日：2002-03-26

申请号：AU9089501

申请日：2001-09-14

Applicant: ATHEROS COMM INC

Inventor： KUSKIN JEFFREY SCOTT ,  NG TAO-FEI SAMUEL ,  DHAMDHERE DEEPAK PRABHAKAR ,  CAIN FIONA J ,  DAVIDSON ANDREW M

IPC: H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/12

Abstract: A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieved from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.

公开(公告)号：AU8908401A

公开(公告)日：2002-03-26

申请号：AU8908401

申请日：2001-09-14

Applicant: ATHEROS COMM INC

Inventor： KUSKIN JEFFREY SCOTT ,  NG TAO-FEI SAMUEL ,  DAVIDSON ANDREW M

IPC: H04L29/06 ,  H04L29/00

Abstract: A Hardware MAC (Media Access Control) unit implements time-critical functions according the 802.11 standard for telecommunications, thereby enhancing system performance. The MAC layer includes three sub-layers: MLME (MAC Sublayer Management Entity), which connects the MAC unit with the host CPU, FTM (Frame Transition Manager), which connects the MAC unit with the network, and FLPM (Frame Level Protocol Manager), which internally connects the MLME sub-layer with the FTM sub-layer. In particular, the FLPM manager includes time-critical and non-time-critical functions that are customarily implemented in software on the MAC by a MAC CPU (Central Processing Unit). The hardware MAC implements time-critical FLPM functions in hardware on the MAC and implements non-time-critical FLPM functions in software on the host CPU so that requirements for processing software on the MAC preferably may be altogether eliminated or alternatively may be substantially reduced.

公开(公告)号：AU2003245257A1

公开(公告)日：2003-11-17

申请号：AU2003245257

申请日：2003-05-02

Applicant: ATHEROS COMM INC

Inventor： KUSKIN JEFFREY SCOTT ,  CHESSON GREGORY L

IPC: H04L12/28 ,  H04L12/56

Abstract: In a preferred embodiment is described a scheduling architecture, including a plurality of queues each within an associated queue control unit, and a plurality of data control units. The queue control units are directed to operations that obtain data for transmission of a stream from a host and ensure that it is available for transmission, preferably as a single stream. The data control units are each directed to operations that format the data from the queue control units in dependence upon the transmission (or channel) characteristics that are to be associated with that data. Further, each queue control unit can configurably be input to any of the data control units. In one embodiment the output of each of the data control units is controlled by a data arbiter, so that a single stream of data is obtained.

公开(公告)号：AU9091801A

公开(公告)日：2002-03-26

申请号：AU9091801

申请日：2001-09-12

Applicant: ATHEROS COMM INC

Inventor： DAVIDSON ANDREW M ,  NG TAO-FEI S ,  KUSKIN JEFFREY SCOTT ,  DHAMDHERE DEEPAK PRABHAKAR ,  CAIN FIONA J

IPC: H04L12/28 ,  H04L29/08 ,  H04W24/00 ,  H04W28/10 ,  H04W72/12 ,  H04W84/18 ,  H04L12/00

Abstract: Systems and methods to provide ordered transmission of data packets to multiple destinations are presented. A transmission device includes a transmitter, a data packet ordering unit, a state table, and a transmit management interface such as a hardware/software unit. The state table stores a transmit block status of each destination. The transmit management interface is coupled to the transmitter and analyzes data packets. The transmit management interface determines whether to transmit a data packet targeted to a particular destination or to block transmission of data packets to the particular destination by examining the transmit block status of the particular destination from the state table.

公开(公告)号：DE60141968D1

公开(公告)日：2010-06-10

申请号：DE60141968

申请日：2001-09-12

Applicant: ATHEROS COMM INC

Inventor： DAVIDSON ANDREW M ,  NG TAO-FEI S ,  KUSKIN JEFFREY SCOTT ,  DHAMDHERE DEEPAK PRABHAKAR ,  CAIN FIONA J

IPC: H04L12/28 ,  H04W28/12 ,  H04L29/08 ,  H04W24/00 ,  H04W28/10 ,  H04W72/12 ,  H04W84/18

Abstract: Systems and methods to provide ordered transmission of data packets to multiple destinations are presented. A transmission device includes a transmitter, a data packet ordering unit, a state table, and a transmit management interface such as a hardware/software unit. The state table stores a transmit block status of each destination. The transmit management interface is coupled to the transmitter and analyzes data packets. The transmit management interface determines whether to transmit a data packet targeted to a particular destination or to block transmission of data packets to the particular destination by examining the transmit block status of the particular destination from the state table.

公开(公告)号：AT341140T

公开(公告)日：2006-10-15

申请号：AT03738894

申请日：2003-05-02

Applicant: ATHEROS COMM INC

Inventor： CHESSON GREGORY L ,  KUSKIN JEFFREY SCOTT

IPC: H04L12/28 ,  H04L12/56

Abstract: In a preferred embodiment is described a scheduling architecture, including a plurality of queues each within an associated queue control unit, and a plurality of data control units. The queue control units are directed to operations that obtain data for transmission of a stream from a host and ensure that it is available for transmission, preferably as a single stream. The data control units are each directed to operations that format the data from the queue control units in dependence upon the transmission (or channel) characteristics that are to be associated with that data. Further, each queue control unit can configurably be input to any of the data control units. In one embodiment the output of each of the data control units is controlled by a data arbiter, so that a single stream of data is obtained.

公开(公告)号：CA2422476A1

公开(公告)日：2002-03-21

申请号：CA2422476

申请日：2001-09-14

Applicant: ATHEROS COMM INC

Inventor： DHAMDHERE DEEPAK PRABHAKAR ,  DAVIDSON ANDREW M ,  NG TAO-FEI SAMUEL ,  KUSKIN JEFFREY SCOTT ,  CAIN FIONA J

IPC: H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/12

Abstract: A key-caching system retrieves actively used keys from a relatively fast cac he memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieve from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.

公开(公告)号：EP1379958A4

公开(公告)日：2009-06-10

申请号：EP02761999

申请日：2002-04-04

Applicant: ATHEROS COMM INC

Inventor： KUSKIN JEFFREY SCOTT ,  NG TAO-FEI SAMUEL ,  DAVIDSON ANDREW M

IPC: G06F13/30 ,  H04L12/56 ,  G06F13/14 ,  G06F13/26

CPC classification number: H04L47/6215 ,  G06F13/30 ,  H04L47/50 ,  H04L47/564 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

Abstract: A method of queue management includes: adding entries having a first priority to a first software queue (34); adding entries having a second priority to a second software queue (36); reading entries from the first software queue to a physical queue; at a threshold time, flushing entries from the physical queue (42); at a threshold time, flushing entries from the physical queue, after the act of flushing the physical queue, reading entries from the second software queue to the physical queue until a termination criterion is satisfied; after the termination criterion is satisfied, reading entries from the first software queue to the physical queue; and transmitting entries from the physical queue to a network (44).

Abstract translation: 队列管理的方法包括：将具有第一优先级的条目添加到第一软件队列; 将具有第二优先级的条目添加到第二软件队列; 将条目从第一个软件队列读取到物理队列; 在阈值时间，从物理队列刷新条目; 在刷新物理队列的行为之后，从第二个软件队列读取条目到物理队列，直到满足终止标准; 在满足终止标准之后，从第一个软件队列读取条目到物理队列; 并将条目从物理队列发送到网络。

公开(公告)号：WO0223853A9

公开(公告)日：2003-04-03

申请号：PCT/US0128705

申请日：2001-09-14

Applicant: ATHEROS COMM INC

Inventor： KUSKIN JEFFREY SCOTT ,  NG TAO-FEI SAMUEL ,  DAVIDSON ANDREW M

IPC: H04L29/06 ,  H04L12/28

CPC classification number: H04L63/162

Abstract: A Hardware MAC (Media Access Control) unit implements time-critical functions according the 802.11 standard for telecommunications, thereby enhancing system performance. The MAC layer includes three sub-layers: MLME (MAC Sublayer Management Entity), which connects the MAC unit with the host CPU, FTM (Frame Transition Manager), which connects the MAC unit with the network, and FLPM (Frame Level Protocol Manager), which internally connects the MLME sub-layer with the FTM sub-layer. In particular, the FLPM manager includes time-critical and non-time-critical functions that are customarily implemented in software on the MAC by a MAC CPU (Central Processing Unit). The hardware MAC implements time-critical FLPM functions in hardware on the MAC and implements non-time-critical FLPM functions in software on the host CPU so that requirements for processing software on the MAC preferably may be altogether eliminated or alternatively may be substantially reduced.

Abstract translation: 硬件MAC（媒体访问控制）单元根据802.11电信标准执行时间关键功能，从而提高系统性能。 MAC层包括三个子层：将MAC单元与主机CPU连接的MLME（MAC子层管理实体），将MAC单元与网络连接的FTM（帧过渡管理器）和FLPM（帧级协议管理器 ），其内部连接MLME子层与FTM子层。 特别地，FLPM管理器包括通过MAC CPU（中央处理单元）在MAC上的软件中通常实现的时间关键和非时间关键功能。 硬件MAC在MAC上的硬件中实现时间关键的FLPM功能，并且在主机CPU上的软件中实现非时间关键的FLPM功能，所以优选地，可以完全消除对MAC上的处理软件的要求，或者可以大大减少。

公开(公告)号：WO0223867A3

公开(公告)日：2003-01-16

申请号：PCT/US0128696

申请日：2001-09-14

Applicant: ATHEROS COMM INC

Inventor： KUSKIN JEFFREY SCOTT ,  NG TAO-FEI SAMUEL ,  DHAMDHERE DEEPAK PRABHAKAR ,  CAIN FIONA J ,  DAVIDSON ANDREW M

IPC: H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/12

CPC classification number: H04L63/0428 ,  H04L1/1829 ,  H04L29/06 ,  H04L29/12783 ,  H04L61/35 ,  H04L63/062 ,  H04L63/164 ,  H04L69/12 ,  H04W8/26 ,  H04W12/02 ,  H04W12/04 ,  H04W84/12

Abstract: A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieve from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.

Abstract translation: 密钥缓存系统从相对较快的高速缓冲存储器中检索主动使用的密钥，用于无线通信的快速处理。 附加键存储在具有高存储容量的相对较慢的系统存储器中。 随着密钥变得需要主动使用，密钥从系统存储器中检索并存储在高速缓冲存储器中。 通过使用主动使用的主动内存，可以提高系统性能。 通过对未使用的密钥使用系统内存，可以使用更多数量的密钥来传输到缓存和随后的主动使用。