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公开(公告)号：AU2002230977A1
公开(公告)日：2002-07-08
申请号：AU2002230977
申请日：2001-12-17
Applicant: ATHEROS COMM INC
Inventor： ZARGARI MASOUND , YUE CHIK PATRICK , SU DAVID K , WEBER DAVID J
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2.发明申请SYNTHESIZER WITH LOCK DETECTOR, LOCK ALGORITHM, EXTENDED RANGE VCO, AND A SIMPLIFIED DUAL MODULUS DIVIDER 审中-公开具有锁定检测器，锁定算法，扩展范围VCO和简化双模块分路器的合成器
公开(公告)号：WO02052728A3
公开(公告)日：2003-11-20
申请号：PCT/US0148874
申请日：2001-12-17
Applicant: ATHEROS COMM INC
Inventor： SU DAVID K , YUE CHIK PATRICK , WEBER DAVID J , ZARGARI MASOUND
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
Abstract translation: 本发明提供一种合成器，其具有有效的锁定检测信号发生器，能够在由多个相邻区域限定的多个相邻特性曲线中的任何一个中操作的扩展范围VCO，以及仅使用单个计数器实现的除法电路 与解码器。 这允许操作合成器的方法，使用扩展范围VCO建立或重新建立锁定条件的方法，以及设计多个除法电路的方法，每个除法电路使用相同的单个计数器并且每个使用不同的解码器。
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