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    Cmos transceiver having an integrated power amplifier
    1.
    发明专利
    Cmos transceiver having an integrated power amplifier 未知

    公开(公告)号：AU9088601A

    公开(公告)日：2002-03-26

    申请号：AU9088601

    申请日：2001-09-14

    Applicant: ATHEROS COMM INC

    Inventor： WEBER DAVID J ,  YUE PATRICK ,  SU DAVID

    IPC: H01L23/66 ,  H01L27/088 ,  H03F1/22 ,  H03F1/52 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45 ,  H04B1/04

    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

    SYNTHESIZER WITH LOCK DETECTOR, LOCK ALGORITHM, EXTENDED RANGE VCO, AND A SIMPLIFIED DUAL MODULUS DIVIDER
    3.
    发明申请
    SYNTHESIZER WITH LOCK DETECTOR, LOCK ALGORITHM, EXTENDED RANGE VCO, AND A SIMPLIFIED DUAL MODULUS DIVIDER 审中-公开
    具有锁定检测器，锁定算法，扩展范围VCO和简化双模块分路器的合成器

    公开(公告)号：WO02052728A3

    公开(公告)日：2003-11-20

    申请号：PCT/US0148874

    申请日：2001-12-17

    Applicant: ATHEROS COMM INC

    Inventor： SU DAVID K ,  YUE CHIK PATRICK ,  WEBER DAVID J ,  ZARGARI MASOUND

    IPC: H03K23/66 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/183 ,  H03L7/193

    CPC classification number: H03L7/099 ,  H03K23/667 ,  H03L7/089 ,  H03L7/095 ,  H03L7/10 ,  H03L7/193 ,  Y10S331/02

    Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

    Abstract translation: 本发明提供一种合成器，其具有有效的锁定检测信号发生器，能够在由多个相邻区域限定的多个相邻特性曲线中的任何一个中操作的扩展范围VCO，以及仅使用单个计数器实现的除法电路 与解码器。 这允许操作合成器的方法，使用扩展范围VCO建立或重新建立锁定条件的方法，以及设计多个除法电路的方法，每个除法电路使用相同的单个计数器并且每个使用不同的解码器。

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