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    Rf integrated circuit layout
    1.
    发明专利
    Rf integrated circuit layout 未知

    公开(公告)号：AU6151101A

    公开(公告)日：2001-11-26

    申请号：AU6151101

    申请日：2001-05-10

    Applicant: ATHEROS COMM INC

    Inventor： YUE CHIK PATRICK ,  ZARGARI MASOUD ,  SU DAVID

    IPC: H01L23/552 ,  H01L23/66

    Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

    Planar inductor with segmented conductive plane
    2.
    发明专利
    Planar inductor with segmented conductive plane 未知

    公开(公告)号：AU2591902A

    公开(公告)日：2002-07-01

    申请号：AU2591902

    申请日：2001-11-06

    Applicant: ATHEROS COMM INC

    Inventor： YUE CHIK PATRICK

    IPC: H01F41/04 ,  H01F17/00 ,  H01F27/36

    Abstract: An integrated circuit inductor structure has a substrate disposed below an inductor. The structure also has plural conductive segments located between the substrate and the inductor. The conductive segments connect at substantially a point below the center of the inductor. An insulating layer lies between the inductor and the conductive segments.

    RF INTEGRATED CIRCUIT LAYOUT
    4.
    发明申请
    RF INTEGRATED CIRCUIT LAYOUT 审中-公开
    RF集成电路布局

    公开(公告)号：WO0188956A3

    公开(公告)日：2002-03-28

    申请号：PCT/US0115399

    申请日：2001-05-10

    Applicant: ATHEROS COMM INC ,  YUE CHIK PATRICK ,  ZARGARI MASOUD ,  SU DAVID

    Inventor： YUE CHIK PATRICK ,  ZARGARI MASOUD ,  SU DAVID

    IPC: H01L23/552 ,  H01L23/66 ,  H01L27/095 ,  H01L23/48 ,  H01L23/58 ,  H01L27/10 ,  H01L29/76

    CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

    Abstract translation: 描述了射频（RF）集成电路。 在一个实施例中，IC包括在非外延衬底上形成多个晶体管的多个金属层。 晶体管是阶梯式和镜面对称的。 此外，RF信号线位于所有其它金属层上的顶部金属层上，并且电源和接地平面位于所有其它金属层下方的底部金属层上。 顶部和底部金属层被屏蔽层隔开，该屏蔽件延伸超过RF信号线一段至少与屏蔽层远离RF线路的距离至少相等的距离。 低频信号位于顶部金属层下方的信号线上。

    SYNTHESIZER WITH LOCK DETECTOR, LOCK ALGORITHM, EXTENDED RANGE VCO, AND A SIMPLIFIED DUAL MODULUS DIVIDER
    5.
    发明申请
    SYNTHESIZER WITH LOCK DETECTOR, LOCK ALGORITHM, EXTENDED RANGE VCO, AND A SIMPLIFIED DUAL MODULUS DIVIDER 审中-公开
    具有锁定检测器，锁定算法，扩展范围VCO和简化双模块分路器的合成器

    公开(公告)号：WO02052728A3

    公开(公告)日：2003-11-20

    申请号：PCT/US0148874

    申请日：2001-12-17

    Applicant: ATHEROS COMM INC

    Inventor： SU DAVID K ,  YUE CHIK PATRICK ,  WEBER DAVID J ,  ZARGARI MASOUND

    IPC: H03K23/66 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/183 ,  H03L7/193

    CPC classification number: H03L7/099 ,  H03K23/667 ,  H03L7/089 ,  H03L7/095 ,  H03L7/10 ,  H03L7/193 ,  Y10S331/02

    Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

    Abstract translation: 本发明提供一种合成器，其具有有效的锁定检测信号发生器，能够在由多个相邻区域限定的多个相邻特性曲线中的任何一个中操作的扩展范围VCO，以及仅使用单个计数器实现的除法电路 与解码器。 这允许操作合成器的方法，使用扩展范围VCO建立或重新建立锁定条件的方法，以及设计多个除法电路的方法，每个除法电路使用相同的单个计数器并且每个使用不同的解码器。

    PLANAR INDUCTOR WITH SEGMENTED CONDUCTIVE PLANE
    6.
    发明申请
    PLANAR INDUCTOR WITH SEGMENTED CONDUCTIVE PLANE 审中-公开
    具有分段导电平面的平面电感器

    公开(公告)号：WO0250848A3

    公开(公告)日：2002-08-29

    申请号：PCT/US0146575

    申请日：2001-11-06

    Applicant: ATHEROS COMM INC

    Inventor： YUE CHIK PATRICK

    IPC: H01F41/04 ,  H01F17/00 ,  H01F27/36

    CPC classification number: H01F17/0006 ,  H01F27/362

    Abstract: An integrated circuit inductor structure has a substrate disposed below an inductor. The structure also has plural conductive segments located between the substrate and the inductor. The conductive segments connect at substantially a point below the center of the inductor. An insulating layer lies between the inductor and the conductive segments.

    Abstract translation: 集成电路电感器结构具有设置在电感器下方的衬底。 该结构还具有位于衬底和电感器之间的多个导电段。 导电段大致在电感器中心的下方连接。 绝缘层位于电感器和导电段之间。

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