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    SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD THEREFOR AND MEMORY
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD THEREFOR AND MEMORY 有权

    公开(公告)号：US20230061246A1

    公开(公告)日：2023-03-02

    申请号：US17857219

    申请日：2022-07-05

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Xiaoguang WANG ,  Dinggui ZENG ,  Huihui LI ,  Kanyu CAO

    IPC: H01L27/22 ,  H01L43/12

    Abstract: A semiconductor structure, a manufacturing method therefor and a memory are provided. The semiconductor structure may at least include: a plurality of aligned transistors, in which the transistors share a same source plate, channels of the transistors are located above the source plate, the channel length direction of the transistors is perpendicular to a surface of the source plate, and a material of the channels includes a single crystal semiconductor; a plurality of drain contacts, electrically connected with drains of the transistors, in which even number of the transistors share one same drain contact; and a plurality of magnetic tunnel junctions, located on the drain contacts and electrically connected with the drain contacts in one-to-one correspondence.

    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    4.
    发明公开
    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20230171969A1

    公开(公告)日：2023-06-01

    申请号：US17827799

    申请日：2022-05-30

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  Beijing Superstring Academy of Memory Technology

    Inventor： Xiaoguang WANG ,  Huihui LI ,  Wei CHANG ,  Kanyu CAO

    IPC: H01L27/105

    CPC classification number: H01L27/1052

    Abstract: Embodiment provides a semiconductor structure and a fabrication method thereof, and relates to the field of semiconductor technology. The fabrication method includes providing a substrate including a peripheral circuit region and an array region having a memory cell, where the peripheral circuit region includes a first region and a second region. In the present disclosure, a logic device configured to control the memory cell and a magnetic memory device are simultaneously fabricated in the peripheral circuit region by means of a process for fabricating a dynamic random access memory (DRAM), such that the same semiconductor structure has two types of memory structures at the same time. Compared with a technology for fabricating two types of memory structures separately, fabricating steps can be simplified, and fabricating costs can be reduced.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE
    8.
    发明公开
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20230171971A1

    公开(公告)日：2023-06-01

    申请号：US17853877

    申请日：2022-06-29

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  Beijing Superstring Academy of Memory Technology

    Inventor： Xiaoguang WANG ,  Huihui LI ,  Qiang ZHANG ,  Minmin WU ,  Shan WANG

    IPC: H01L27/105

    CPC classification number: H01L27/1052

    Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate including a first array region and a second array region. The first array region is provided with a first memory array comprising a plurality of first memory structures, and the second array region is provided with a second memory array comprising a plurality of second memory structures. Compared with related technologies where different memory structures are stacked on a substrate, in this embodiment, the plurality of first memory structures and the plurality of second memory structures are arranged side by side on the substrate, which is advantageous to simplifying fabrication processes and improving production efficiency.

    VERTICAL TRANSISTOR, STORAGE UNIT AND MANUFACTURING METHOD THEREFOR
    10.
    发明申请
    VERTICAL TRANSISTOR, STORAGE UNIT AND MANUFACTURING METHOD THEREFOR 有权

    公开(公告)号：US20250031411A1

    公开(公告)日：2025-01-23

    申请号：US18714965

    申请日：2022-12-07

    Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

    Inventor： Huihui LI ,  Yunsen ZHANG ,  Guilei WANG ,  Chao ZHAO

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00 ,  H10B61/00

    Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

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