公开(公告)号：US20240130106A1

公开(公告)日：2024-04-18

申请号：US18304219

申请日：2023-04-20

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jin DAI ,  Yong YU ,  Jing LIANG

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.