公开(公告)号：US20230171939A1

公开(公告)日：2023-06-01

申请号：US17818537

申请日：2022-08-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan XIAO ,  Yong YU ,  Guangsu SHAO

IPC: H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10891 ,  H01L27/10885

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

公开(公告)号：US20230363136A1

公开(公告)日：2023-11-09

申请号：US17931888

申请日：2022-09-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan XIAO ,  Yong YU ,  Guangsu SHAO

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10814 ,  H01L27/10852

Abstract: A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.

公开(公告)号：US20230171942A1

公开(公告)日：2023-06-01

申请号：US17818509

申请日：2022-08-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan XIAO ,  Yong YU ,  Guangsu SHAO

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10814 ,  H01L27/10885

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars on the substrate, where each of the active pillars includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

公开(公告)号：US20240130106A1

公开(公告)日：2024-04-18

申请号：US18304219

申请日：2023-04-20

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jin DAI ,  Yong YU ,  Jing LIANG

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

公开(公告)号：US20230170416A1

公开(公告)日：2023-06-01

申请号：US17817412

申请日：2022-08-04

Applicant: CHANGXIN MEMORY TECHNOLOGIES, ICC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan XIAO ,  Yong YU ,  Guangsu SHAO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L27/108

CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66666

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; preprocessing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.