公开(公告)号：US20250071968A1

公开(公告)日：2025-02-27

申请号：US18754367

申请日：2024-06-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xuezheng AI ,  Xiangsheng WANG ,  Guilei WANG ,  Chao ZHAO ,  Wenhua GUI

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

公开(公告)号：US20240381626A1

公开(公告)日：2024-11-14

申请号：US18695254

申请日：2023-08-21

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xuezheng AI ,  Xiangsheng WANG ,  Guilei WANG ,  Chao ZHAO ,  Jin DAI ,  Wenhua GUI

IPC: H10B12/00

Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

公开(公告)号：US20250056790A1

公开(公告)日：2025-02-13

申请号：US18754418

申请日：2024-06-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Wenhua GUI ,  Xuezheng AI ,  Guilei WANG ,  Jin DAI ,  Xiangsheng WANG

IPC: H10B12/00

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.