公开(公告)号：EP4380330A1

公开(公告)日：2024-06-05

申请号：EP22955194.0

申请日：2022-12-07

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： DAI, Jin ,  YU, Yong ,  LIANG, Jing

IPC: H10B12/00

Abstract: The present disclosure provides a memory cell, a 3D memory and a preparation thereof, and an electronic device, and relates to the technical field of semiconductor technology. The memory cell includes a first transistor and a second transistor disposed on a substrate (1), the first transistor includes a first gate (11), a first electrode (33), a second electrode (34) and a first semiconductor layer (6) disposed on the substrate; the second transistor includes a third electrode (51) , a fourth electrode (52), a second gate (12) extending in a direction perpendicular to the substrate (1) and a second semiconductor layer (9) surrounding a sidewall of the second gate (12) which are disposed on the substrate (1), the second semiconductor layer (9) includes a second source contact region (91) and a second drain contact region (92) arranged at intervals, a channel between the second source contact region (91) and the second drain contact region (92) is a horizontal channel.

公开(公告)号：EP4375823A1

公开(公告)日：2024-05-29

申请号：EP22952885.6

申请日：2022-12-19

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： DAI, Jin ,  ZHANG, Yunsen

IPC: G06F3/06

CPC classification number: Y02D10/00

Abstract: An object computing and storage system, a data processing method, and a client and a storage medium, which belong to the field of electrical digital data processing. The object computing and storage system comprises a storage control device, and a storage chip or a storage disk which is connected thereto, wherein the storage control device is a computing and storage management system and executes the following processing: receiving an external data processing request, and parsing information of a specified storage object, information of a specified function and information of input data, which pieces of information are carried in the data processing request; when it is determined that calling of the specified function for the specified storage object is supported, calling the specified function according to the input data to perform computation on data of the specified storage object; and returning a computation result to a sender of the data processing request.

公开(公告)号：EP4380329A1

公开(公告)日：2024-06-05

申请号：EP22955193.2

申请日：2022-12-07

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： DAI, Jin ,  YU, Yong ,  LIANG, Jing

IPC: H10B12/00 ,  H01L29/786

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate (1), and a word line (110). A memory cell includes a transistor which includes a source (51) and a drain (52), a gate (11) extending in the direction perpendicular to the substrate (1), a semiconductor layer (9) surrounding a sidewall of the gate (11). The semiconductor layer (9) includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line (110) extends in the direction perpendicular to the substrate (1) and penetrates through the memory cells of different layers.

公开(公告)号：EP4375842A1

公开(公告)日：2024-05-29

申请号：EP23853680.9

申请日：2023-04-04

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： DAI, Jin ,  ZHANG, Yunsen

IPC: G06F13/42 ,  G06F3/06

CPC classification number: Y02D10/00

Abstract: A storage system and a computational storage processor thereof, a solid-state drive and data reading and writing methods. The storage system includes a solid-state drive (SSD) and a computational storage processor (CSP), and communication between the SSD and the CSP, communication between the SSD and the external of the storage system, and communication between the CSP and the external of the storage system are performed through a point-to-point communication protocol of a peripheral component interconnect express (PCIe) bus; the CSP is configured to receive a first operation instruction based on a storage object from the external, generate a second operation instruction based on a flash memory address according to information carried by the first operation instruction and SSD resource information maintained locally, and send the second operation instruction to the SSD; and the SSD is configured to, after receiving the second operation instruction, exchange the data of the storage object with the external according to information carried by the second operation instruction.