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公开(公告)号:EP1018134A4
公开(公告)日:2001-02-21
申请号:EP98944670
申请日:1998-09-02
Applicant: CANDESCENT TECH CORP
Inventor: HANSEN RONALD L , FRIEDMAN JAY
CPC classification number: G09G3/2011 , G09G3/22 , G09G2310/0267 , G09G2310/027 , G09G2320/043 , G09G2320/0606 , G09G2320/0666
Abstract: A circuit and method for controlling the color balance of a flat panel display without losing gray scale resolution of the display screen. Within a FED screen (200), a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are activated sequentially by row drivers (220a-220c) and corresponding individual gray scale information (voltages) is driven over the columns by column drivers (240-240c). When the proper voltage is applied across the cathode and anode of the emitters, they release electrons toward a phosphor spot, e.g., red, green, blue, causing an illumination point. Within each column driver (240a-240c), a digital to analog converter (340a-340c) contains two data-in voltage-out transformation functions, a first function corresponding to a first voltage intensity and a second function corresponding to a lesser voltage intensity for a same digital color value.
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公开(公告)号:EP1074015A4
公开(公告)日:2001-11-07
申请号:EP98961963
申请日:1998-12-07
Applicant: CANDESCENT TECH CORP
Inventor: HANSEN RONALD L , FRIEDMAN JAY , FREIBERG PAUL
CPC classification number: G09G3/22 , G09G3/2011 , G09G2310/027 , G09G2320/043 , G09G2320/0606 , G09G2320/0626 , G09G2320/0666
Abstract: A circuit and method for time multiplexing a voltage signal for controlling the color balance of a flat panel display, Field Emission Display (200). Row drivers (220) are sequentially activated during 'row on-time windows' and corresponding individual gray scale information (voltage) are driven by column drivers (240). In one embodiment, within each column driver (240a(i)), a first error compensation circuit (810a(i)), during the first frame of each frame pair, divides the first voltage data and generates a second voltage data having a negative error, and a second error compensation circuit (820a(i)) during the second frame of each frame pair generates a second voltage data having a positive error. Selection circuitry for driving a first voltage data during a first part of the row on-time window and a second voltage data during a second part of the row on-time window comprises multiplexers (830a(i) and 834a(i)), output register (320(i)), decoder (330a(i)), digital-to-analog converter (340a(i)), channel amplifier (370a(i)).
Abstract translation: 一种用于时间多路复用电压信号以控制平板显示器的色彩平衡的电路和方法,场发射显示器(200)。 行驱动器(220)在“行开启时间窗”期间被顺序地激活,并且对应的单独灰度级信息(电压)由列驱动器(240)驱动。 在一个实施例中,在每个帧对的第一帧期间,第一误差补偿电路(810a(i))在每个列驱动器(240a(i))内分割第一电压数据并且生成具有负的第二电压数据 误差,并且在每个帧对的第二帧期间第二误差补偿电路(820a(i))产生具有正误差的第二电压数据。 用于在行导通时间窗的第一部分期间驱动第一电压数据的选择电路和在行导通时间窗的第二部分期间的第二电压数据包括多路复用器(830a(i)和834a(i)),输出 (320a(i)),解码器(330a(i)),数模转换器(340a(i)),信道放大器(370a(i))。
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公开(公告)号:EP1066618A4
公开(公告)日:2001-11-07
申请号:EP98960800
申请日:1998-12-07
Applicant: CANDESCENT TECH CORP
Inventor: HANSEN RONALD L , FRIEDMAN JAY , STOIAN LEE
CPC classification number: G09G3/22 , G09G3/2011 , G09G2310/027 , G09G2320/043 , G09G2320/0606 , G09G2320/0626 , G09G2320/0666
Abstract: A circuit for time multiplexing a voltage signal for controlling the color balance of a flat panel display (200). Within an FED screen, a matrix of rows (230) and columns (250) is provided and emitters are situated within each row-column intersection (100). Rows are sequentially activated during 'row on-time windows' by row drivers (220) and corresponding individual gray scale information (voltages) are driven over the columns by column drivers (240). Within each column driver, the present invention provides selection circuitry for driving a first voltage signal during a first part of the row on-time window and a second voltage during a second part of the row on-time window. The lengths of the first part and second part of the row on-time window can be adjusted for a given color, to adjust the color balance with respect to color.
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