公开(公告)号：EP1066618A4

公开(公告)日：2001-11-07

申请号：EP98960800

申请日：1998-12-07

Applicant: CANDESCENT TECH CORP

Inventor： HANSEN RONALD L ,  FRIEDMAN JAY ,  STOIAN LEE

IPC: G09G3/20 ,  G09G3/22 ,  G09G3/32

CPC classification number: G09G3/22 ,  G09G3/2011 ,  G09G2310/027 ,  G09G2320/043 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2320/0666

Abstract: A circuit for time multiplexing a voltage signal for controlling the color balance of a flat panel display (200). Within an FED screen, a matrix of rows (230) and columns (250) is provided and emitters are situated within each row-column intersection (100). Rows are sequentially activated during 'row on-time windows' by row drivers (220) and corresponding individual gray scale information (voltages) are driven over the columns by column drivers (240). Within each column driver, the present invention provides selection circuitry for driving a first voltage signal during a first part of the row on-time window and a second voltage during a second part of the row on-time window. The lengths of the first part and second part of the row on-time window can be adjusted for a given color, to adjust the color balance with respect to color.