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    PRODUCTION OF WARM-MIX ASPHALT COMPOSITIONS UTILIZING A POLYHYDRIC ALCOHOL
    1.
    发明专利
    PRODUCTION OF WARM-MIX ASPHALT COMPOSITIONS UTILIZING A POLYHYDRIC ALCOHOL 未知

    公开(公告)号：CA2662497A1

    公开(公告)日：2009-10-17

    申请号：CA2662497

    申请日：2009-04-15

    Applicant: CARLSON DAVID A

    Inventor： CARLSON DAVID A

    IPC: C08L95/00 ,  C08J3/20 ,  C08K3/00 ,  C08K5/053 ,  C08K9/10 ,  C08L9/06 ,  C08L71/02

    Abstract: Rubber particles in a water and polyhydric alcohol solution are added to an asphalt whereby the polyhydric alcohol substantially coats the rubber particles resulting in an easily mixed composition with the mixing temperature being reduced to a rang e of from about 250.degree.F to about 310.degree.F resulting in considerable ener gy savings. In a similar manner, a filler can be substantially coated by polyvinyl alcohol- water solution and the same blended with an asphalt and mixed at reduced temperatures. Another embodiment relates to the utilization of a polyhydric alcohol that is added to an asphalt and mixed therewith at reduced temperatures.

    DIRECT ACCESS TO LOW-LATENCY MEMORY
    3.
    发明申请
    DIRECT ACCESS TO LOW-LATENCY MEMORY 审中-公开
    直接访问低延迟存储器

    公开(公告)号：WO2006031462A9

    公开(公告)日：2006-08-24

    申请号：PCT/US2005031295

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    Inventor： BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    IPC: G06F9/312 ,  G06F12/08

    CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

    Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    Abstract translation: 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

    MULTIPLY INSTRUCTIONS FOR MODULAR EXPONENTIATION
    4.
    发明申请
    MULTIPLY INSTRUCTIONS FOR MODULAR EXPONENTIATION 审中-公开
    用于模块化指示的多重指令

    公开(公告)号：WO2006029152A3

    公开(公告)日：2006-09-14

    申请号：PCT/US2005031709

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  CARLSON DAVID A

    Inventor： CARLSON DAVID A

    IPC: G06F7/52

    CPC classification number: G06F7/527 ,  G06F7/723 ,  G06F9/3001 ,  G06F9/30065 ,  G06F9/30112 ,  G06F9/383

    Abstract: A method and apparatus for increasing performance of a multiplication operation in a processor. The processor's instruction set includes multiply instructions that can be used to accelerate modular exponentiation. Prior to issuing a sequence of multiply instructions for the multiplication operation, a multiplier register in a multiply unit in the processor is loaded with the value of the multiplier. The multiply unit stores intermediate results of the multiplication operation in redundant format. The intermediate results are shifted and stored in the product register in the multiply unit so that carries between intermediate results are handled within the multiply unit.

    Abstract translation: 一种用于提高处理器中的乘法运算的性能的方法和设备。 处理器的指令集包含可用于加速模幂运算的乘法指令。 在为乘法运算发出一系列乘法指令之前，处理器乘法单元中的乘法器寄存器加载乘法器的值。 乘法单元以冗余格式存储乘法运算的中间结果。 中间结果被移位并存储在乘法单元的乘积寄存器中，以便在乘法单元内处理中间结果之间的载荷。

    SELECTIVE REPLICATION OF DATA STRUCTURE
    5.
    发明申请
    SELECTIVE REPLICATION OF DATA STRUCTURE 审中-公开
    数据结构的选择性复制

    公开(公告)号：WO2006031551A2

    公开(公告)日：2006-03-23

    申请号：PCT/US2005031803

    申请日：2005-09-09

    Applicant: CAVIUM NETWORKS ,  BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E

    Inventor： BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E

    CPC classification number: G06F12/06 ,  G06F12/0653 ,  G06F2212/174

    Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data, structures that are loaded (i.e., read) more often than they are stored (i.e., written).

    Abstract translation: 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储器组。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和其他数据，比它们被存储（即写入）更多的载体（即读）的结构。

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