公开(公告)号：US20140120715A1

公开(公告)日：2014-05-01

申请号：US14147891

申请日：2014-01-06

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hui Chen

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16058 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers.

Abstract translation: 半导体制造方法包括提供具有金属层的载体，其中所述金属层包括多个基底区域和多个外部横向区域; 形成第一光致抗蚀剂层; 形成多个轴承部; 移除第一光致抗蚀剂层以露出轴承部分，每个轴承部分包括具有第一区域和第二区域的支承表面; 形成用于露出所述支承表面的第一区域的第二光致抗蚀剂层; 形成多个连接部，其中，所述支承面的所述第一区域被所述连接部覆盖，以使每个连接部分与每个支承部分连接以形成卡扣凸块; 去除金属层的外侧面区域，以使基部区域形成多个凸起下的冶金层。

公开(公告)号：US20140117540A1

公开(公告)日：2014-05-01

申请号：US14148038

申请日：2014-01-06

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hui Chen

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers.