公开(公告)号：US3511923A

公开(公告)日：1970-05-12

申请号：US3511923D

申请日：1968-02-08

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT ,  BIZET PIERRE

IPC: H04L12/12 ,  H01L7/02

CPC classification number: H04L12/12 ,  Y02D50/40

Abstract: 1,154,678. Telegraphy; transistor pulse circuits. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 14 Feb., 1968 [14 Feb., 1967], No. 7189/68. Headings H3T and H4P. An unattended telegraph terminal is switched to receiver data at one or other of two speeds by a received control signal having a duration of at least t2. Data on line 10 passes through either unit 11 or 12 to output 13, units 11, 12 being enabled alternatively by bi-stable 36. The data also passes to differentiator 23, 25 and via inverter 21 to differentiator 22, 24. Thus any transition in the input data places a positive pulse on transistor 28 which discharges capacitor 30. If now a control signal, consisting of all Mark or all Space, is received capacitor 30 has time (at least t2) to charge sufficiently to break down uni-junction transistor 31. The resulting signal passes via unit 35 to set bi-stable 36 to one or other stable state. Unit 35 is controlled by relay 35 which is fed by all received signals. Thus if a long Mark signal is received, lasting at least a time t2, relay 34 will direct the unijunction signal to contact b and unit 12 will be enabled. A long Space signal enables unit 11 similarly. The duration of the control signal is chosen to exceed the duration of the longest all Mark or all Space signal occurring in normal information transmission.

公开(公告)号：US3500213A

公开(公告)日：1970-03-10

申请号：US3500213D

申请日：1967-06-05

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT

IPC: H04L27/12 ,  H03B19/00

CPC classification number: H04L27/12 ,  H04L27/122

公开(公告)号：DE1512172A1

公开(公告)日：1969-07-17

申请号：DE1512172

申请日：1967-06-01

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT

IPC: H04L27/12 ,  H03B19/00

Abstract: 1,180,418. Frequency dividers; telegraphy. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 5 June, 1967 [3 June, 1966], No. 25817/67. Headings H3F and H4P. [Also in Division G4] In a frequency-shift telegraphy system errors due to flutter are proportional to the frequencies used and are reduced by modulating high frequencies which are divided down to provide low transmission frequencies. In Fig. 1 a data source 1 is coupled through a filter 2 to cause a multivibrator 3 to operate at one of two output frequencies. The multivibrator feeds a reversible counter 6 which counts from 0 to 15 and is coupled to a decoder 7 which provides corresponding outputs at terminals 0-15 feeding a digital-to-analogue converter 8 which supplies an output voltage proportional to where i is the number of the input terminal actuated. The terminals 0 and 15 are connected to a bi-stable 5 connected to the control terminals of the counter 6 so that the counter counts from 0 to 15 and then reverses and so on, the output of converter 8 then being a stepped sine wave which is smoothed either in the output amplifier 9 or in a subsequent filter (not shown). In a modified arrangement, Fig. 3 (not shown), the counter counts from 0 to 7, and a further bi-stable reverses the sign of the output of the digital-to-analogue converter after each complete up-and-down counting cycle. In this circuit the input is also different, the data input being used to allow the output of one or other of two separate oscillators to pass to the counter.

公开(公告)号：FR1381263A

公开(公告)日：1964-12-14

申请号：FR934617

申请日：1963-05-13

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT

IPC: H03B19/14 ,  H03K3/286 ,  H03K23/00

公开(公告)号：DE2334527A1

公开(公告)日：1974-01-24

申请号：DE2334527

申请日：1973-07-06

Applicant: CIT ALCATEL

Inventor： BOYER MARCELLOUIS ,  AMEAU ALBERT ,  HEBERT FRANCOIS

IPC: H04L1/24 ,  H04L25/04

Abstract: 1416963 Distortion correction in data transmission systems; transistor switching circuits COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 5 July 1973 [10 July 1972] 32191/73 Headings H4P and H3T A bipolar coded data transmission line corrector which selects, from n correctors, that one which supplies the least bipolarity errors comprising means for sequentially connecting the n correctors in circuit and detecting the respective errors is characterized by the provision of means for storing and comparing the errors detected with each corrector and a logic circuit for subsequently connecting in circuit the corrector given the minimum error. Correctors C1, C2, C3 are sequentially connected in circuit between A, A 1 and at the same time, the respective errors on line D are sequentially applied via delays M1, M2, M3 and counters K1, K2, K3 to stores Y1, Y2, Y3. The three stored signals are then compared in amplifiers A1, A2 to produce outputs on lines E, F which are either positive or negative depending on which stored signal is the smallest. Signals E, F are then applied to circuit 35 to produce corresponding outputs b1, b2, b3 which connect into circuit the corrector C1, C2, or C3 which gave the minimum error. Comparator details.-If V2 is smaller than V1 transistor Q is cut off and relay R remains deenergized applying a negative signal to input E of circuit 35, and connecting V2 to the positive input of amplifier A2. If V1 is smaller than V2 transistor Q conducts, energizing relay R to apply a positive signal to input E and to connect V1 to the positive input of A2. The polarity of signal F will then depend on whether signal V3 is greater or less than the signal (V1 or V2) with which it is being compared. Circuit 35 details, Fig. 3-If F is positive, transistor Q1 is switched on by a pulse from source 30 to set bi-stable B3 producing output b3 and transistors Q5, Q6 are held non-conducting to prevent bi-stables B1 or B2 being set. If F is negative, the state of B3 allows Q5, Q6 to conduct. Application of a positive signal E then. turns on Q7 to set bi-stable B1 and application. of a negative signal E turns on Q8 to set bistable B2.

公开(公告)号：FR1518887A

公开(公告)日：1968-03-29

申请号：FR94927

申请日：1967-02-14

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT ,  BIZET PIERRE

IPC: H04L12/12

公开(公告)号：FR2283593A1

公开(公告)日：1976-03-26

申请号：FR7426597

申请日：1974-07-31

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT ,  STENSTROM CLAUDE ,  MINARD FRANCIS

IPC: H03K9/06

Abstract: The digital demodulator is for transmissions modulated in phase or frequency by a data source. The design is intended to simplify the complex filter system normally associated with demultiplexing transmissions carried on post office telephone lines. An analogue to digital converter (3) is followed by a discriminator circuit (T) feeding an output demultiplexing stage, the three major stages being preceeded by an input level regulator and a band pass filter with a cut-off at 4KHz. The discriminator has three basic units, a computing circuit providing a discrimination signal for each route, an equalising band pass filter and a sampling type unit reproducing the telegraphy signals.

公开(公告)号：FR1496141A

公开(公告)日：1967-09-29

申请号：FR64071

申请日：1966-06-03

Applicant: CIT ALCATEL

Inventor： AMEAU ALBERT

IPC: H04L27/12

Abstract: 1,180,418. Frequency dividers; telegraphy. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 5 June, 1967 [3 June, 1966], No. 25817/67. Headings H3F and H4P. [Also in Division G4] In a frequency-shift telegraphy system errors due to flutter are proportional to the frequencies used and are reduced by modulating high frequencies which are divided down to provide low transmission frequencies. In Fig. 1 a data source 1 is coupled through a filter 2 to cause a multivibrator 3 to operate at one of two output frequencies. The multivibrator feeds a reversible counter 6 which counts from 0 to 15 and is coupled to a decoder 7 which provides corresponding outputs at terminals 0-15 feeding a digital-to-analogue converter 8 which supplies an output voltage proportional to where i is the number of the input terminal actuated. The terminals 0 and 15 are connected to a bi-stable 5 connected to the control terminals of the counter 6 so that the counter counts from 0 to 15 and then reverses and so on, the output of converter 8 then being a stepped sine wave which is smoothed either in the output amplifier 9 or in a subsequent filter (not shown). In a modified arrangement, Fig. 3 (not shown), the counter counts from 0 to 7, and a further bi-stable reverses the sign of the output of the digital-to-analogue converter after each complete up-and-down counting cycle. In this circuit the input is also different, the data input being used to allow the output of one or other of two separate oscillators to pass to the counter.